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[88.112.131.206]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2fd536a2d1fsm2347011fa.140.2024.10.30.04.15.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 30 Oct 2024 04:15:36 -0700 (PDT) Message-ID: Date: Wed, 30 Oct 2024 13:15:35 +0200 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 3/6] media: qcom: camss: Add support for camss driver on SC7280 Content-Language: en-US To: Vikram Sharma , rfoss@kernel.org, todor.too@gmail.com, bryan.odonoghue@linaro.org, mchehab@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, akapatra@quicinc.com, hariramp@quicinc.com, andersson@kernel.org, konradybcio@kernel.org, hverkuil-cisco@xs4all.nl, cros-qcom-dts-watchers@chromium.org, catalin.marinas@arm.com, will@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@quicinc.com References: <20241030105347.2117034-1-quic_vikramsa@quicinc.com> <20241030105347.2117034-4-quic_vikramsa@quicinc.com> From: Vladimir Zapolskiy In-Reply-To: <20241030105347.2117034-4-quic_vikramsa@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 10/30/24 12:53, Vikram Sharma wrote: > From: Suresh Vankadara > > Add support for the camss driver on the SC7280 SoC. > > Signed-off-by: Suresh Vankadara > Signed-off-by: Trishansh Bhardwaj > Signed-off-by: Vikram Sharma > --- > .../media/platform/qcom/camss/camss-csid.c | 1 - > .../qcom/camss/camss-csiphy-3ph-1-0.c | 5 + > .../media/platform/qcom/camss/camss-csiphy.c | 5 + > .../media/platform/qcom/camss/camss-csiphy.h | 1 + > drivers/media/platform/qcom/camss/camss-vfe.c | 2 + > drivers/media/platform/qcom/camss/camss.c | 339 ++++++++++++++++++ > drivers/media/platform/qcom/camss/camss.h | 1 + > 7 files changed, 353 insertions(+), 1 deletion(-) > > diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c > index 858db5d4ca75..8d3dc26e2af4 100644 > --- a/drivers/media/platform/qcom/camss/camss-csid.c > +++ b/drivers/media/platform/qcom/camss/camss-csid.c > @@ -1028,7 +1028,6 @@ int msm_csid_subdev_init(struct camss *camss, struct csid_device *csid, > csid->res->hw_ops->subdev_init(csid); > > /* Memory */ > - > if (camss->res->version == CAMSS_8250) { > /* for titan 480, CSID registers are inside the VFE region, > * between the VFE "top" and "bus" registers. this requires > diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > index 7d2490c9de01..f341f7b7fd8a 100644 > --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > @@ -505,6 +505,10 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy, > u32 val; > > switch (csiphy->camss->res->version) { > + case CAMSS_7280: > + r = &lane_regs_sm8250[0][0]; > + array_size = ARRAY_SIZE(lane_regs_sm8250[0]); > + break; > case CAMSS_8250: > r = &lane_regs_sm8250[0][0]; > array_size = ARRAY_SIZE(lane_regs_sm8250[0]); > @@ -557,6 +561,7 @@ static bool csiphy_is_gen2(u32 version) > bool ret = false; > > switch (version) { > + case CAMSS_7280: > case CAMSS_8250: > case CAMSS_8280XP: > case CAMSS_845: > diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/media/platform/qcom/camss/camss-csiphy.c > index 68a3ea1ba2a5..9722cee4143f 100644 > --- a/drivers/media/platform/qcom/camss/camss-csiphy.c > +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c > @@ -108,6 +108,11 @@ const struct csiphy_formats csiphy_formats_sdm845 = { > .formats = formats_sdm845 > }; > > +const struct csiphy_formats csiphy_formats_sc7280 = { > + .nformats = ARRAY_SIZE(formats_sdm845), > + .formats = formats_sdm845 > +}; > + Since you are picky about alphabetical sorting, you may need to keep it here as well. > /* > * csiphy_get_bpp - map media bus format to bits per pixel > * @formats: supported media bus formats array > diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/media/platform/qcom/camss/camss-csiphy.h > index eebc1ff1cfab..67a96ef55bb6 100644 > --- a/drivers/media/platform/qcom/camss/camss-csiphy.h > +++ b/drivers/media/platform/qcom/camss/camss-csiphy.h > @@ -112,6 +112,7 @@ void msm_csiphy_unregister_entity(struct csiphy_device *csiphy); > extern const struct csiphy_formats csiphy_formats_8x16; > extern const struct csiphy_formats csiphy_formats_8x96; > extern const struct csiphy_formats csiphy_formats_sdm845; > +extern const struct csiphy_formats csiphy_formats_sc7280; Same comment as above. > > extern const struct csiphy_hw_ops csiphy_ops_2ph_1_0; > extern const struct csiphy_hw_ops csiphy_ops_3ph_1_0; > diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c > index ffcb1e2ec417..61f6815a3756 100644 > --- a/drivers/media/platform/qcom/camss/camss-vfe.c > +++ b/drivers/media/platform/qcom/camss/camss-vfe.c > @@ -334,6 +334,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code, > } > break; > case CAMSS_660: > + case CAMSS_7280: > case CAMSS_8x96: > case CAMSS_8250: > case CAMSS_8280XP: > @@ -1692,6 +1693,7 @@ static int vfe_bpl_align(struct vfe_device *vfe) > int ret = 8; > > switch (vfe->camss->res->version) { > + case CAMSS_7280: > case CAMSS_8250: > case CAMSS_8280XP: > case CAMSS_845: > diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c > index e8cd8afe7bee..addaed8f77cb 100644 > --- a/drivers/media/platform/qcom/camss/camss.c > +++ b/drivers/media/platform/qcom/camss/camss.c > @@ -1480,6 +1480,330 @@ static const struct resources_icc icc_res_sc8280xp[] = { > }, > }; > > +static const struct camss_subdev_resources csiphy_res_7280[] = { Same comment as above. > + /* CSIPHY0 */ > + { > + .regulators = {}, > + .clock = { "csiphy0", "csiphy0_timer"}, > + .clock_rate = { > + { 300000000 }, > + { 300000000 } > + }, > + .reg = { "csiphy0" }, > + .interrupt = { "csiphy0" }, > + .csiphy = { > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sc7280 > + } > + }, > + /* CSIPHY1 */ > + { > + .regulators = {}, > + .clock = { "csiphy1", "csiphy1_timer"}, > + .clock_rate = { > + { 300000000 }, > + { 300000000 } > + }, > + .reg = { "csiphy1" }, > + .interrupt = { "csiphy1" }, > + .csiphy = { > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sc7280 > + } > + }, > + /* CSIPHY2 */ > + { > + .regulators = {}, > + .clock = { "csiphy2", "csiphy2_timer"}, > + .clock_rate = { > + { 300000000 }, > + { 300000000 } > + }, > + .reg = { "csiphy2" }, > + .interrupt = { "csiphy2" }, > + .csiphy = { > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sc7280 > + } > + }, > + /* CSIPHY3 */ > + { > + .regulators = {}, > + .clock = { "csiphy3", "csiphy3_timer"}, > + .clock_rate = { > + { 300000000 }, > + { 300000000 } > + }, > + .reg = { "csiphy3" }, > + .interrupt = { "csiphy3" }, > + .csiphy = { > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sc7280 > + } > + }, > + /* CSIPHY4 */ > + { > + .regulators = {}, > + .clock = { "csiphy4", "csiphy4_timer"}, > + .clock_rate = { > + { 300000000 }, > + { 300000000 } > + }, > + .reg = { "csiphy4" }, > + .interrupt = { "csiphy4" }, > + .csiphy = { > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sc7280 > + } > + }, > +}; > + > +static const struct camss_subdev_resources csid_res_7280[] = { > + /* CSID0 */ > + { > + .regulators = { "vdda-phy", "vdda-pll" }, Supply regulators shall be properties of CSIPHY IP and its representation in the driver. > + > + .clock = { "csi0", "vfe0_cphy_rx", "vfe0", "soc_ahb"}, > + .clock_rate = { > + { 300000000, 0, 380000000, 0}, > + { 400000000, 0, 510000000, 0}, > + { 400000000, 0, 637000000, 0}, > + { 400000000, 0, 760000000, 0} > + }, > + > + .reg = { "csid0" }, > + .interrupt = { "csid0" }, > + .csid = { > + .is_lite = false, > + .hw_ops = &csid_ops_gen2, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .formats = &csid_formats_gen2 > + } > + }, > + /* CSID1 */ > + { > + .regulators = { "vdda-phy", "vdda-pll" }, > + > + .clock = { "csi1", "vfe1_cphy_rx", "vfe1", "soc_ahb"}, > + .clock_rate = { > + { 300000000, 0, 380000000, 0}, > + { 400000000, 0, 510000000, 0}, > + { 400000000, 0, 637000000, 0}, > + { 400000000, 0, 760000000, 0} > + }, > + > + .reg = { "csid1" }, > + .interrupt = { "csid1" }, > + .csid = { > + .is_lite = false, > + .hw_ops = &csid_ops_gen2, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .formats = &csid_formats_gen2 > + } > + }, > + /* CSID2 */ > + { > + .regulators = { "vdda-phy", "vdda-pll" }, > + > + .clock = { "csi2", "vfe2_cphy_rx", "vfe2", "soc_ahb"}, > + .clock_rate = { > + { 300000000, 0, 380000000, 0}, > + { 400000000, 0, 510000000, 0}, > + { 400000000, 0, 637000000, 0}, > + { 400000000, 0, 760000000, 0} > + }, > + > + .reg = { "csid2" }, > + .interrupt = { "csid2" }, > + .csid = { > + .is_lite = false, > + .hw_ops = &csid_ops_gen2, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .formats = &csid_formats_gen2 > + } > + }, > + /* CSID3 */ > + { > + .regulators = { "vdda-phy", "vdda-pll" }, > + > + .clock = { "csi3", "vfe0_lite_cphy_rx", "vfe0_lite", "soc_ahb"}, > + .clock_rate = { > + { 300000000, 0, 320000000, 0}, > + { 400000000, 0, 400000000, 0}, > + { 400000000, 0, 480000000, 0}, > + { 400000000, 0, 600000000, 0} > + }, > + > + .reg = { "csid_lite0" }, > + .interrupt = { "csid_lite0" }, > + .csid = { > + .is_lite = true, > + .hw_ops = &csid_ops_gen2, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .formats = &csid_formats_gen2 > + } > + }, > + /* CSID4 */ > + { > + .regulators = { "vdda-phy", "vdda-pll" }, > + > + .clock = { "csi3", "vfe0_lite_cphy_rx", "vfe0_lite", "soc_ahb"}, > + .clock_rate = { > + { 300000000, 0, 320000000, 0}, > + { 400000000, 0, 400000000, 0}, > + { 400000000, 0, 480000000, 0}, > + { 400000000, 0, 600000000, 0} > + }, > + > + .reg = { "csid_lite1" }, > + .interrupt = { "csid_lite1" }, > + .csid = { > + .is_lite = true, > + .hw_ops = &csid_ops_gen2, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .formats = &csid_formats_gen2 > + } > + }, > +}; > + > +static const struct camss_subdev_resources vfe_res_7280[] = { > + /* VFE0 */ > + { > + .regulators = {}, > + > + .clock = { "vfe0", "vfe0_axi", "soc_ahb", > + "camnoc_axi", "gcc_camera_axi"}, > + .clock_rate = { > + { 380000000, 0, 80000000, 150000000, 0}, > + { 510000000, 0, 80000000, 240000000, 0}, > + { 637000000, 0, 80000000, 320000000, 0}, > + { 760000000, 0, 80000000, 400000000, 0}, > + { 760000000, 0, 80000000, 480000000, 0}, > + }, > + > + .reg = { "vfe0" }, > + .interrupt = { "vfe0" }, > + .vfe = { > + .line_num = 3, > + .is_lite = false, > + .has_pd = true, > + .pd_name = "ife0", > + .hw_ops = &vfe_ops_170, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > + /* VFE1 */ > + { > + .regulators = {}, > + > + .clock = { "vfe1", "vfe1_axi", "soc_ahb", > + "camnoc_axi", "gcc_camera_axi"}, > + .clock_rate = { > + { 380000000, 0, 80000000, 150000000, 0}, > + { 510000000, 0, 80000000, 240000000, 0}, > + { 637000000, 0, 80000000, 320000000, 0}, > + { 760000000, 0, 80000000, 400000000, 0}, > + { 760000000, 0, 80000000, 480000000, 0}, > + }, > + > + .reg = { "vfe1" }, > + .interrupt = { "vfe1" }, > + .vfe = { > + .line_num = 3, > + .is_lite = false, > + .has_pd = true, > + .pd_name = "ife1", > + .hw_ops = &vfe_ops_170, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > + /* VFE2 */ > + { > + .regulators = {}, > + > + .clock = { "vfe2", "vfe2_axi", "soc_ahb", > + "camnoc_axi", "gcc_camera_axi"}, > + .clock_rate = { > + { 380000000, 0, 80000000, 150000000, 0}, > + { 510000000, 0, 80000000, 240000000, 0}, > + { 637000000, 0, 80000000, 320000000, 0}, > + { 760000000, 0, 80000000, 400000000, 0}, > + { 760000000, 0, 80000000, 480000000, 0}, > + }, > + > + .reg = { "vfe2" }, > + .interrupt = { "vfe2" }, > + .vfe = { > + .line_num = 3, > + .is_lite = false, > + .hw_ops = &vfe_ops_170, > + .has_pd = true, > + .pd_name = "ife2", > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > + /* VFE3 (lite) */ > + { > + .clock = { "vfe0_lite", "soc_ahb", > + "camnoc_axi", "gcc_camera_axi"}, > + .clock_rate = { > + { 320000000, 80000000, 150000000, 0}, > + { 400000000, 80000000, 240000000, 0}, > + { 480000000, 80000000, 320000000, 0}, > + { 600000000, 80000000, 400000000, 0}, > + }, > + > + .regulators = {}, > + .reg = { "vfe_lite0" }, > + .interrupt = { "vfe_lite0" }, > + .vfe = { > + .line_num = 4, > + .is_lite = true, > + .hw_ops = &vfe_ops_170, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > + /* VFE4 (lite) */ > + { > + .clock = { "vfe1_lite", "soc_ahb", > + "camnoc_axi", "gcc_camera_axi"}, > + .clock_rate = { > + { 320000000, 80000000, 150000000, 0}, > + { 400000000, 80000000, 240000000, 0}, > + { 480000000, 80000000, 320000000, 0}, > + { 600000000, 80000000, 400000000, 0}, > + }, > + > + .regulators = {}, > + .reg = { "vfe_lite1" }, > + .interrupt = { "vfe_lite1" }, > + .vfe = { > + .line_num = 4, > + .is_lite = true, > + .hw_ops = &vfe_ops_170, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > +}; > + > +static const struct resources_icc icc_res_sc7280[] = { > + { > + .name = "ahb", > + .icc_bw_tbl.avg = 38400, > + .icc_bw_tbl.peak = 76800, > + }, > + { > + .name = "hf_0", > + .icc_bw_tbl.avg = 2097152, > + .icc_bw_tbl.peak = 2097152, > + }, > +}; > + > /* > * camss_add_clock_margin - Add margin to clock frequency rate > * @rate: Clock frequency rate > @@ -2453,9 +2777,24 @@ static const struct camss_resources sc8280xp_resources = { > .link_entities = camss_link_entities > }; > > +static const struct camss_resources sc7280_resources = { > + .version = CAMSS_7280, > + .pd_name = "top", > + .csiphy_res = csiphy_res_7280, > + .csid_res = csid_res_7280, > + .vfe_res = vfe_res_7280, > + .icc_res = icc_res_sc7280, > + .icc_path_num = ARRAY_SIZE(icc_res_sc7280), > + .csiphy_num = ARRAY_SIZE(csiphy_res_7280), > + .csid_num = ARRAY_SIZE(csid_res_7280), > + .vfe_num = ARRAY_SIZE(vfe_res_7280), > + .link_entities = camss_link_entities > +}; > + > static const struct of_device_id camss_dt_match[] = { > { .compatible = "qcom,msm8916-camss", .data = &msm8916_resources }, > { .compatible = "qcom,msm8996-camss", .data = &msm8996_resources }, > + { .compatible = "qcom,sc7280-camss", .data = &sc7280_resources }, > { .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources }, > { .compatible = "qcom,sdm660-camss", .data = &sdm660_resources }, > { .compatible = "qcom,sdm845-camss", .data = &sdm845_resources }, > diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h > index 0ce84fcbbd25..bbdf9aa81c36 100644 > --- a/drivers/media/platform/qcom/camss/camss.h > +++ b/drivers/media/platform/qcom/camss/camss.h > @@ -80,6 +80,7 @@ enum camss_version { > CAMSS_8x16, > CAMSS_8x96, > CAMSS_660, > + CAMSS_7280, > CAMSS_845, > CAMSS_8250, > CAMSS_8280XP, -- Best wishes, Vladimir