From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71916C25B50 for ; Tue, 24 Jan 2023 01:32:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230062AbjAXBc3 (ORCPT ); Mon, 23 Jan 2023 20:32:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55628 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232119AbjAXBcZ (ORCPT ); Mon, 23 Jan 2023 20:32:25 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75F4B12869 for ; Mon, 23 Jan 2023 17:32:24 -0800 (PST) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 30O16FQk022142; Tue, 24 Jan 2023 01:32:18 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=qcppdkim1; bh=vF95dqDa/R8Z7yyWDXCxH0fMBaAqtseYAnS+hvjIqBM=; b=lJbJiPf25dM+gujGtrk65lXrOj4KYVWZDlGUMu/w76NubyXZwsTGOq/g3ap1ctEdqLOL 0L7zxwYXauSqUvBNrLBOv1RzxYmwkGOzlT/Hi04lqumxytpvTRNnuhY9K8ol4aZCGXV5 psD9MoGvP7dLA79gyg/mhC4X/LQZBrQo2xcQScbLZJje1GEf2rl9wlXWgqFu98pFXAdJ rBSXqTS6qv/bJOHqRNp5DfpIB5IRBe9rSrH9loS81mZX0HhfS8TJx40W//uMp4moFxBY q5h3ePrQSAXv8pR5V8Qz3kH4QlBmzQptjwCz+CKCrtaiQwEILF2vJutEnc6rXet13Tl6 iQ== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3n89frc72n-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 24 Jan 2023 01:32:18 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 30O1WGt2000490 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 24 Jan 2023 01:32:16 GMT Received: from [10.110.62.90] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Mon, 23 Jan 2023 17:32:15 -0800 Message-ID: Date: Mon, 23 Jan 2023 17:32:14 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.2 Subject: Re: [PATCH] drm/msm/dpu: disable features unsupported by QCM2290 Content-Language: en-US To: Dmitry Baryshkov , Rob Clark , Sean Paul CC: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , , , , Loic Poulain References: <20230123071145.3056242-1-dmitry.baryshkov@linaro.org> From: Abhinav Kumar In-Reply-To: <20230123071145.3056242-1-dmitry.baryshkov@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: eaT3OLy9J7XBKL7rJUkyzPF1KNcMbRbD X-Proofpoint-GUID: eaT3OLy9J7XBKL7rJUkyzPF1KNcMbRbD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-01-23_12,2023-01-23_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=991 lowpriorityscore=0 phishscore=0 malwarescore=0 suspectscore=0 adultscore=0 impostorscore=0 priorityscore=1501 spamscore=0 bulkscore=0 mlxscore=0 clxscore=1011 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301240010 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 1/22/2023 11:11 PM, Dmitry Baryshkov wrote: > QCM2290 doesn't seem to support reg-dma, smart-dma, UBWC, CDP, exclusion > rectangles and CSC. Drop corresponding features being incorrectly > enabled for qcm2290. > Can you please point me to which vendor DT you are referring to for this? CSC is supported on the VIG SSPPs from what I can see. QCM2290 should be using the same MDP version as 6115 from the HW version. > Cc: Loic Poulain > Fixes: 5334087ee743 ("drm/msm: add support for QCM2290 MDSS") > Signed-off-by: Dmitry Baryshkov > --- > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 +++++++++++-------- > 1 file changed, 12 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 289fb11f99d1..1c3ffa922794 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -12,10 +12,14 @@ > #include "dpu_hw_catalog.h" > #include "dpu_kms.h" > > -#define VIG_MASK \ > +#define VIG_BASE_MASK \ > (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\ > + BIT(DPU_SSPP_TS_PREFILL)) > + > +#define VIG_MASK \ > + (VIG_BASE_MASK | \ > BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) |\ > - BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT)) > + BIT(DPU_SSPP_EXCL_RECT)) > > #define VIG_MSM8998_MASK \ > (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3)) > @@ -29,7 +33,7 @@ > #define VIG_SM8250_MASK \ > (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE)) > > -#define VIG_QCM2290_MASK (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL)) > +#define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL)) > > #define DMA_MSM8998_MASK \ > (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\ > @@ -50,6 +54,10 @@ > #define DMA_CURSOR_MSM8998_MASK \ > (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR)) > > +#define DMA_QCM2290_MASK \ > + (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ > + BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1)) > + > #define MIXER_MSM8998_MASK \ > (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER)) > > @@ -316,8 +324,6 @@ static const struct dpu_caps msm8998_dpu_caps = { > static const struct dpu_caps qcm2290_dpu_caps = { > .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, > .max_mixer_blendstages = 0x4, > - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, > - .ubwc_version = DPU_HW_UBWC_VER_20, > .has_dim_layer = true, > .has_idle_pc = true, > .max_linewidth = 2160, > @@ -1384,7 +1390,7 @@ static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1); > static const struct dpu_sspp_cfg qcm2290_sspp[] = { > SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_QCM2290_MASK, > qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), > - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, > + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_QCM2290_MASK, > qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), > }; > > @@ -2836,8 +2842,6 @@ static const struct dpu_mdss_cfg qcm2290_dpu_cfg = { > .intf = qcm2290_intf, > .vbif_count = ARRAY_SIZE(sdm845_vbif), > .vbif = sdm845_vbif, > - .reg_dma_count = 1, > - .dma_cfg = &sdm845_regdma, > .perf = &qcm2290_perf_data, > .mdss_irqs = IRQ_SC7180_MASK, > };