[PATCH 0/3] arm64: dts: qcom: sc7280: Add the MDSS_CORE reset

[PATCH 0/3] arm64: dts: qcom: sc7280: Add the MDSS_CORE reset

[Bjorn Andersson]

The version of bootloader found e.g. in the Particle Tachyon configures
the display subsystem to the point that Linux isn't recovering the
state (currently hits one or more iommu faults which results in a panic,
still debugging this).

Introduce the MDSS reset, like we've done on other platforms, to allow
the OS to clear the bootloader state.

Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
---
Bjorn Andersson (3):
      dt-bindings: clock: dispcc-sc7280: Add display resets
      clk: qcom: dispcc-sc7280: Add dispcc resets
      arm64: dts: qcom: sc7280: Add MDSS_CORE reset to mdss

 arch/arm64/boot/dts/qcom/sc7280.dtsi           | 2 ++
 drivers/clk/qcom/dispcc-sc7280.c               | 8 ++++++++
 include/dt-bindings/clock/qcom,dispcc-sc7280.h | 4 ++++
 3 files changed, 14 insertions(+)
---
base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585
change-id: 20250811-sc7280-mdss-reset-a703d4b8a2c4

Best regards,
-- 
Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>

[PATCH 1/3] dt-bindings: clock: dispcc-sc7280: Add display resets

[Bjorn Andersson]

Like other platforms the sc7280 display clock controller provides a
couple of resets, add the defines to allow referring to them.

Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
---
 include/dt-bindings/clock/qcom,dispcc-sc7280.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/dt-bindings/clock/qcom,dispcc-sc7280.h b/include/dt-bindings/clock/qcom,dispcc-sc7280.h
index a4a692c20acfc954251fd1a1a59239ac62b20015..9f113f346be80b8a7815ffb17a6a6ce5e008f663 100644
--- a/include/dt-bindings/clock/qcom,dispcc-sc7280.h
+++ b/include/dt-bindings/clock/qcom,dispcc-sc7280.h
@@ -52,4 +52,8 @@
 /* DISP_CC power domains */
 #define DISP_CC_MDSS_CORE_GDSC				0
 
+/* DISPCC resets */
+#define DISP_CC_MDSS_CORE_BCR				0
+#define DISP_CC_MDSS_RSCC_BCR				1
+
 #endif

-- 
2.49.0

[PATCH 2/3] clk: qcom: dispcc-sc7280: Add dispcc resets

[Bjorn Andersson]

Like many other platforms the sc7280 display clock controller provides
a couple of resets for the display subsystem. In particular the
MDSS_CORE_BCR is useful to reset the display subsystem to a known state
during boot, so add these.

Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
---
 drivers/clk/qcom/dispcc-sc7280.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/clk/qcom/dispcc-sc7280.c b/drivers/clk/qcom/dispcc-sc7280.c
index 8bdf57734a3d47fdf8bd2053640d8ef462677556..465dc06c87128182348a4e0ea384af779647bd84 100644
--- a/drivers/clk/qcom/dispcc-sc7280.c
+++ b/drivers/clk/qcom/dispcc-sc7280.c
@@ -17,6 +17,7 @@
 #include "clk-regmap-divider.h"
 #include "common.h"
 #include "gdsc.h"
+#include "reset.h"
 
 enum {
 	P_BI_TCXO,
@@ -847,6 +848,11 @@ static struct gdsc *disp_cc_sc7280_gdscs[] = {
 	[DISP_CC_MDSS_CORE_GDSC] = &disp_cc_mdss_core_gdsc,
 };
 
+static const struct qcom_reset_map disp_cc_sc7280_resets[] = {
+	[DISP_CC_MDSS_CORE_BCR] = { 0x1000 },
+	[DISP_CC_MDSS_RSCC_BCR] = { 0x2000 },
+};
+
 static const struct regmap_config disp_cc_sc7280_regmap_config = {
 	.reg_bits = 32,
 	.reg_stride = 4,
@@ -861,6 +867,8 @@ static const struct qcom_cc_desc disp_cc_sc7280_desc = {
 	.num_clks = ARRAY_SIZE(disp_cc_sc7280_clocks),
 	.gdscs = disp_cc_sc7280_gdscs,
 	.num_gdscs = ARRAY_SIZE(disp_cc_sc7280_gdscs),
+	.resets = disp_cc_sc7280_resets,
+	.num_resets = ARRAY_SIZE(disp_cc_sc7280_resets),
 };
 
 static const struct of_device_id disp_cc_sc7280_match_table[] = {

-- 
2.49.0

[PATCH 3/3] arm64: dts: qcom: sc7280: Add MDSS_CORE reset to mdss

[Bjorn Andersson]

Like on other platforms, if the OS does not support recovering the state
left by the bootloader it needs access to MDSS_CORE, so that it can
clear the MDSS configuration.

Until now it seems no version of the bootloaders have done so, but e.g.
the Particle Tachyon ships with a bootloader that does leave the display
in a state that results in a series of iommu faults.

So let's provide the reset, to allow the OS to clear that state.

Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 64a2abd3010018e94eb50c534a509d6b4cf2473b..5eafcb84cd452ecc758922b69774837e9f5a899a 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -4724,6 +4724,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
 
 			iommus = <&apps_smmu 0x900 0x402>;
 
+			resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
 			#address-cells = <2>;
 			#size-cells = <2>;
 			ranges;

-- 
2.49.0

Re: [PATCH 2/3] clk: qcom: dispcc-sc7280: Add dispcc resets

[Taniya Das]

On 8/12/2025 8:41 AM, Bjorn Andersson wrote:
> Like many other platforms the sc7280 display clock controller provides
> a couple of resets for the display subsystem. In particular the
> MDSS_CORE_BCR is useful to reset the display subsystem to a known state
> during boot, so add these.
> 

In this issue I believe the requirement is to have a clean sheet and
restart the MDSS explicitly. Historically MDSS never required a BCR reset.

> Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
> ---
>  drivers/clk/qcom/dispcc-sc7280.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/clk/qcom/dispcc-sc7280.c b/drivers/clk/qcom/dispcc-sc7280.c
> index 8bdf57734a3d47fdf8bd2053640d8ef462677556..465dc06c87128182348a4e0ea384af779647bd84 100644
> --- a/drivers/clk/qcom/dispcc-sc7280.c
> +++ b/drivers/clk/qcom/dispcc-sc7280.c
> @@ -17,6 +17,7 @@
>  #include "clk-regmap-divider.h"
>  #include "common.h"
>  #include "gdsc.h"
> +#include "reset.h"
>  
>  enum {
>  	P_BI_TCXO,
> @@ -847,6 +848,11 @@ static struct gdsc *disp_cc_sc7280_gdscs[] = {
>  	[DISP_CC_MDSS_CORE_GDSC] = &disp_cc_mdss_core_gdsc,
>  };
>  
> +static const struct qcom_reset_map disp_cc_sc7280_resets[] = {
> +	[DISP_CC_MDSS_CORE_BCR] = { 0x1000 },
> +	[DISP_CC_MDSS_RSCC_BCR] = { 0x2000 },
> +};
> +
>  static const struct regmap_config disp_cc_sc7280_regmap_config = {
>  	.reg_bits = 32,
>  	.reg_stride = 4,
> @@ -861,6 +867,8 @@ static const struct qcom_cc_desc disp_cc_sc7280_desc = {
>  	.num_clks = ARRAY_SIZE(disp_cc_sc7280_clocks),
>  	.gdscs = disp_cc_sc7280_gdscs,
>  	.num_gdscs = ARRAY_SIZE(disp_cc_sc7280_gdscs),
> +	.resets = disp_cc_sc7280_resets,
> +	.num_resets = ARRAY_SIZE(disp_cc_sc7280_resets),
>  };
>  
>  static const struct of_device_id disp_cc_sc7280_match_table[] = {
> 

Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>

-- 
Thanks,
Taniya Das

Re: [PATCH 1/3] dt-bindings: clock: dispcc-sc7280: Add display resets

[Taniya Das]

On 8/12/2025 8:41 AM, Bjorn Andersson wrote:
> Like other platforms the sc7280 display clock controller provides a
> couple of resets, add the defines to allow referring to them.
> 
> Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
> ---
>  include/dt-bindings/clock/qcom,dispcc-sc7280.h | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/include/dt-bindings/clock/qcom,dispcc-sc7280.h b/include/dt-bindings/clock/qcom,dispcc-sc7280.h
> index a4a692c20acfc954251fd1a1a59239ac62b20015..9f113f346be80b8a7815ffb17a6a6ce5e008f663 100644
> --- a/include/dt-bindings/clock/qcom,dispcc-sc7280.h
> +++ b/include/dt-bindings/clock/qcom,dispcc-sc7280.h
> @@ -52,4 +52,8 @@
>  /* DISP_CC power domains */
>  #define DISP_CC_MDSS_CORE_GDSC				0
>  
> +/* DISPCC resets */
> +#define DISP_CC_MDSS_CORE_BCR				0
> +#define DISP_CC_MDSS_RSCC_BCR				1
> +
>  #endif
> 

Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>

-- 
Thanks,
Taniya Das

Re: [PATCH 3/3] arm64: dts: qcom: sc7280: Add MDSS_CORE reset to mdss

[Konrad Dybcio]

On 8/12/25 5:11 AM, Bjorn Andersson wrote:
> Like on other platforms, if the OS does not support recovering the state
> left by the bootloader it needs access to MDSS_CORE, so that it can
> clear the MDSS configuration.
> 
> Until now it seems no version of the bootloaders have done so, but e.g.
> the Particle Tachyon ships with a bootloader that does leave the display
> in a state that results in a series of iommu faults.
> 
> So let's provide the reset, to allow the OS to clear that state.
> 
> Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH 2/3] clk: qcom: dispcc-sc7280: Add dispcc resets

[Bjorn Andersson]

On Tue, Aug 12, 2025 at 10:35:30AM +0530, Taniya Das wrote:
> 
> 
> On 8/12/2025 8:41 AM, Bjorn Andersson wrote:
> > Like many other platforms the sc7280 display clock controller provides
> > a couple of resets for the display subsystem. In particular the
> > MDSS_CORE_BCR is useful to reset the display subsystem to a known state
> > during boot, so add these.
> > 
> 
> In this issue I believe the requirement is to have a clean sheet and
> restart the MDSS explicitly. Historically MDSS never required a BCR reset.
> 

On most targets we rely on the display driver coming up and configuring
the hardware anew in a way that happens to be aligned with the existing
state (boot splash) - or there was no state, which makes this easier.

But I had to introduce the use of the BCR reset in compute platforms
when I worked on DP, because some of the state left by the bootloader
would conflict with what Linux was doing. Similar on this target, as
we're trying to initialize the display driver, we get a bunch of iommu
faults.

Ultimately, the display driver should likely read back the hardware
state and attempt a graceful transition between whatever state the
bootloader left the hardware in and what Linux wants it to be.

When this feature is implemented, the display driver can simply stop
pulling the BCR.

> > Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
> > ---
> >  drivers/clk/qcom/dispcc-sc7280.c | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> > 
> > diff --git a/drivers/clk/qcom/dispcc-sc7280.c b/drivers/clk/qcom/dispcc-sc7280.c
> > index 8bdf57734a3d47fdf8bd2053640d8ef462677556..465dc06c87128182348a4e0ea384af779647bd84 100644
> > --- a/drivers/clk/qcom/dispcc-sc7280.c
> > +++ b/drivers/clk/qcom/dispcc-sc7280.c
> > @@ -17,6 +17,7 @@
> >  #include "clk-regmap-divider.h"
> >  #include "common.h"
> >  #include "gdsc.h"
> > +#include "reset.h"
> >  
> >  enum {
> >  	P_BI_TCXO,
> > @@ -847,6 +848,11 @@ static struct gdsc *disp_cc_sc7280_gdscs[] = {
> >  	[DISP_CC_MDSS_CORE_GDSC] = &disp_cc_mdss_core_gdsc,
> >  };
> >  
> > +static const struct qcom_reset_map disp_cc_sc7280_resets[] = {
> > +	[DISP_CC_MDSS_CORE_BCR] = { 0x1000 },
> > +	[DISP_CC_MDSS_RSCC_BCR] = { 0x2000 },
> > +};
> > +
> >  static const struct regmap_config disp_cc_sc7280_regmap_config = {
> >  	.reg_bits = 32,
> >  	.reg_stride = 4,
> > @@ -861,6 +867,8 @@ static const struct qcom_cc_desc disp_cc_sc7280_desc = {
> >  	.num_clks = ARRAY_SIZE(disp_cc_sc7280_clocks),
> >  	.gdscs = disp_cc_sc7280_gdscs,
> >  	.num_gdscs = ARRAY_SIZE(disp_cc_sc7280_gdscs),
> > +	.resets = disp_cc_sc7280_resets,
> > +	.num_resets = ARRAY_SIZE(disp_cc_sc7280_resets),
> >  };
> >  
> >  static const struct of_device_id disp_cc_sc7280_match_table[] = {
> > 
> 
> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
> 

Thanks,
Bjorn

> -- 
> Thanks,
> Taniya Das
> 

Re: (subset) [PATCH 0/3] arm64: dts: qcom: sc7280: Add the MDSS_CORE reset

[Bjorn Andersson]

On Mon, 11 Aug 2025 22:11:32 -0500, Bjorn Andersson wrote:
> The version of bootloader found e.g. in the Particle Tachyon configures
> the display subsystem to the point that Linux isn't recovering the
> state (currently hits one or more iommu faults which results in a panic,
> still debugging this).
> 
> Introduce the MDSS reset, like we've done on other platforms, to allow
> the OS to clear the bootloader state.
> 
> [...]

Applied, thanks!

[3/3] arm64: dts: qcom: sc7280: Add MDSS_CORE reset to mdss
      commit: 9cdb77e3103a449ee54f397d29321a5d4157bcb7

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>