Re: [PATCH v1 0/5] Add snps,dis_u3_susphy_quirk for some QC targets

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 3/25/25 1:30 PM, Prashanth K wrote:
> During device mode initialization on certain QC targets, before the
> runstop bit is set, sometimes it's observed that the GEVNTADR{LO/HI}
> register write fails. As a result, GEVTADDR registers are still 0x0.
> Upon setting runstop bit, DWC3 controller attempts to write the new
> events to address 0x0, causing an SMMU fault and system crash. More
> info about the crash at [1].
> 
> This was initially observed on SM8450 and later reported on few
> other targets as well. As suggested by Qualcomm HW team, clearing
> the GUSB3PIPECTL.SUSPHY bit resolves the issue by preventing register
> write failures. Address this by setting the snps,dis_u3_susphy_quirk
> to keep the GUSB3PIPECTL.SUSPHY bit cleared. This change was tested
> on multiple targets (SM8350, SM8450 QCS615 etc.) for over an year
> and hasn't exhibited any side effects.
> 
> [1]: https://lore.kernel.org/all/fa94cbc9-e637-ba9b-8ec8-67c6955eca98@quicinc.com/
> 
> Prashanth K (3):
>   arm64: dts: qcom: sm8150: Add snps,dis_u3_susphy_quirk
>   arm64: dts: qcom: sm8350: Add snps,dis_u3_susphy_quirk
>   arm64: dts: qcom: sm8450: Add snps,dis_u3_susphy_quirk
> 
> Pratham Pratap (2):
>   arm64: dts: qcom: qcs615: Add snps,dis_u3_susphy_quirk
>   arm64: dts: qcom: qdu1000: Add snps,dis_u3_susphy_quirk

Are there more targets affected, from the list of the ones currently
supported upstream?

Konrad