Re: [PATCH 3/3] clk: qcom: smd: Add missing MSM8998 RPM clocks

[Caleb Connolly <caleb@connolly.tech>]

[tested on Pixel 2 XL]
Tested-by: Caleb Connolly <caleb@connolly.tech>

On 26/02/2022 21:41, Konrad Dybcio wrote:
> Add missing RPM-provided clocks on msm8998 and reorder the definitions
> where needed.
>
> JAMI: fixed for a0384ecfe2aa ("clk: qcom: smd-rpm: De-duplicate identical entries")
> JAMI: fixed for 36354c32bd76 ("clk: qcom: smd-rpm: Add .recalc_rate hook for clk_smd_rpm_branch_ops")
> Tested-by: Jami Kettunen <jami.kettunen@somainline.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> ---
>   drivers/clk/qcom/clk-smd-rpm.c | 40 +++++++++++++++++++++++-----------
>   1 file changed, 27 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
> index 418f017e933f..afc6dc930011 100644
> --- a/drivers/clk/qcom/clk-smd-rpm.c
> +++ b/drivers/clk/qcom/clk-smd-rpm.c
> @@ -816,15 +816,18 @@ static const struct rpm_smd_clk_desc rpm_clk_qcs404 = {
>   	.num_clks = ARRAY_SIZE(qcs404_clks),
>   };
>
> -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin,
> -				     3, 19200000);
> +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000);
> +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin, 3, 19200000);
>   DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc_clk, aggre1_noc_a_clk,
>   		   QCOM_SMD_RPM_AGGR_CLK, 1);
>   DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc_clk, aggre2_noc_a_clk,
>   		   QCOM_SMD_RPM_AGGR_CLK, 2);
>   DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk3, rf_clk3_a, 6, 19200000);
>   DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3_pin, rf_clk3_a_pin, 6, 19200000);
> +
>   static struct clk_smd_rpm *msm8998_clks[] = {
> +	[RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
> +	[RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
>   	[RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
>   	[RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
>   	[RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
> @@ -837,12 +840,22 @@ static struct clk_smd_rpm *msm8998_clks[] = {
>   	[RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
>   	[RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
>   	[RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
> +	[RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
> +	[RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
> +	[RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
> +	[RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
>   	[RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
>   	[RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
>   	[RPM_SMD_LN_BB_CLK1] = &msm8916_bb_clk1,
>   	[RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a,
>   	[RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2,
>   	[RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a,
> +	[RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3,
> +	[RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a,
> +	[RPM_SMD_LN_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
> +	[RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
> +	[RPM_SMD_LN_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
> +	[RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
>   	[RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin,
>   	[RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin,
>   	[RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk,
> @@ -855,10 +868,14 @@ static struct clk_smd_rpm *msm8998_clks[] = {
>   	[RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
>   	[RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
>   	[RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
> -	[RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
> -	[RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
> +	[RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
> +	[RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
>   	[RPM_SMD_RF_CLK3] = &msm8998_rf_clk3,
>   	[RPM_SMD_RF_CLK3_A] = &msm8998_rf_clk3_a,
> +	[RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
> +	[RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
> +	[RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
> +	[RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
>   	[RPM_SMD_RF_CLK3_PIN] = &msm8998_rf_clk3_pin,
>   	[RPM_SMD_RF_CLK3_A_PIN] = &msm8998_rf_clk3_a_pin,
>   };
> @@ -868,9 +885,6 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8998 = {
>   	.num_clks = ARRAY_SIZE(msm8998_clks),
>   };
>
> -DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000);
> -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin, ln_bb_clk3_pin_a, 3, 19200000);
> -
>   static struct clk_smd_rpm *sdm660_clks[] = {
>   	[RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
>   	[RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
> @@ -900,16 +914,16 @@ static struct clk_smd_rpm *sdm660_clks[] = {
>   	[RPM_SMD_LN_BB_A_CLK] = &msm8916_bb_clk1_a,
>   	[RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2,
>   	[RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a,
> -	[RPM_SMD_LN_BB_CLK3] = &sdm660_ln_bb_clk3,
> -	[RPM_SMD_LN_BB_CLK3_A] = &sdm660_ln_bb_clk3_a,
> +	[RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3,
> +	[RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a,
>   	[RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
>   	[RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
>   	[RPM_SMD_LN_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
>   	[RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
>   	[RPM_SMD_LN_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
>   	[RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
> -	[RPM_SMD_LN_BB_CLK3_PIN] = &sdm660_ln_bb_clk3_pin,
> -	[RPM_SMD_LN_BB_CLK3_A_PIN] = &sdm660_ln_bb_clk3_pin_a,
> +	[RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin,
> +	[RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin,
>   };
>
>   static const struct rpm_smd_clk_desc rpm_clk_sdm660 = {
> @@ -1011,8 +1025,8 @@ static struct clk_smd_rpm *sm6125_clks[] = {
>   	[RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a,
>   	[RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2,
>   	[RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a,
> -	[RPM_SMD_LN_BB_CLK3] = &sdm660_ln_bb_clk3,
> -	[RPM_SMD_LN_BB_CLK3_A] = &sdm660_ln_bb_clk3_a,
> +	[RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3,
> +	[RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a,
>   	[RPM_SMD_QUP_CLK] = &sm6125_qup_clk,
>   	[RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk,
>   	[RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk,
> --
> 2.35.1
>

--
Kind Regards,
Caleb