Re: [PATCH] clk: qcom: ipq5332: mark GPLL4 as critical temporarily

[Kathiravan T <quic_kathirav@quicinc.com>]

On 2/1/2023 2:47 AM, Stephen Boyd wrote:
> Quoting Kathiravan Thirumoorthy (2023-01-30 04:09:59)
>> diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
>> index a8ce618bb81b..6159d0e1e43f 100644
>> --- a/drivers/clk/qcom/gcc-ipq5332.c
>> +++ b/drivers/clk/qcom/gcc-ipq5332.c
>> @@ -127,6 +127,7 @@ static struct clk_alpha_pll gpll4_main = {
>>                          .parent_data = &gcc_parent_data_xo,
>>                          .num_parents = 1,
>>                          .ops = &clk_alpha_pll_stromer_ops,
>> +                       .flags = CLK_IS_CRITICAL,
> Please add a comment above this line that indicates why this is
> critical. What clk needs to be added that will actually use this? If
> nothing is ever going to use the PLL then maybe we should simply not
> register this PLL with the clk framework?
Sure, will add the comment in the code also.

There are bunch of WCSS, Q6, QDSS, PCIE clocks uses the GPPL4 as source. 
Few of them are getting disabled by clock framework since there are no 
consumers yet (which will added soon) and few of them are yet to be 
added. So we cannot leave out this PLL. If any one of the consumer is 
enabled, this patch can be reverted.