Re: [PATCH v3 10/13] drm/msm/dpu: remove topology name

[Jeykumar Sankaran <jsanka-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>]

On 2018-08-14 13:14, Sean Paul wrote:
> On Tue, Aug 07, 2018 at 08:20:08PM -0700, Jeykumar Sankaran wrote:
>> Strip down the support for topology enums. It
>> can be replaced with simple hw count checks.
> 
> Can you remove the enum entirely? A quick scan seems like it might be
> possible,
> it seems like it's only used in topology_def to pass to reservations 
> and
> it's
> only used in reservations for log messages. Ofc, I might be missing 
> some
> usage a
> little more buried...
> 
> Sean
> 
The final patch in the series is getting rid of that. This patch just 
removes
the DPU dependency on those enums for getting the topology details.

Jeykumar S
>> 
>> changes in v2:
>> 	- none
>> changes in v3:
>> 	- none
>> 
>> Change-Id: If9b2a4db5bbdf8545b99b6d90825e256d014382d
>> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
>> ---
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c          |  3 ---
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h     |  9 ++++++---
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c |  7 ++++---
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c               | 12 
>> ------------
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h               |  9 ---------
>>  5 files changed, 10 insertions(+), 30 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> index 7b82e2d..58647ed 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> @@ -1019,7 +1019,6 @@ static void dpu_encoder_virt_mode_set(struct
> drm_encoder *drm_enc,
>>  	struct drm_connector *conn = NULL, *conn_iter;
>>  	struct dpu_rm_hw_iter pp_iter, ctl_iter;
>>  	struct msm_display_topology topology;
>> -	enum dpu_rm_topology_name topology_name;
>>  	struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC];
>> 
>>  	int i = 0, ret;
>> @@ -1077,7 +1076,6 @@ static void dpu_encoder_virt_mode_set(struct
> drm_encoder *drm_enc,
>>  		hw_ctl[i] = (struct dpu_hw_ctl *)ctl_iter.hw;
>>  	}
>> 
>> -	topology_name = dpu_rm_get_topology_name(topology);
>>  	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
>>  		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
>> 
>> @@ -1097,7 +1095,6 @@ static void dpu_encoder_virt_mode_set(struct
> drm_encoder *drm_enc,
>>  			phys->hw_ctl = hw_ctl[i];
>> 
>>  			phys->connector = conn->state->connector;
>> -			phys->topology_name = topology_name;
>>  			if (phys->ops.mode_set)
>>  				phys->ops.mode_set(phys, mode, adj_mode);
>>  		}
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
>> index c7df8aa..d08b5d5 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
>> @@ -24,6 +24,7 @@
>>  #include "dpu_hw_top.h"
>>  #include "dpu_hw_cdm.h"
>>  #include "dpu_encoder.h"
>> +#include "dpu_crtc.h"
>> 
>>  #define DPU_ENCODER_NAME_MAX	16
>> 
>> @@ -219,7 +220,6 @@ struct dpu_encoder_irq {
>>   * @split_role:		Role to play in a split-panel
> configuration
>>   * @intf_mode:		Interface mode
>>   * @intf_idx:		Interface index on dpu hardware
>> - * @topology_name:	topology selected for the display
>>   * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes
>>   * @enable_state:	Enable state tracking
>>   * @vblank_refcount:	Reference count of vblank request
>> @@ -249,7 +249,6 @@ struct dpu_encoder_phys {
>>  	enum dpu_enc_split_role split_role;
>>  	enum dpu_intf_mode intf_mode;
>>  	enum dpu_intf intf_idx;
>> -	enum dpu_rm_topology_name topology_name;
>>  	spinlock_t *enc_spinlock;
>>  	enum dpu_enc_enable_state enable_state;
>>  	atomic_t vblank_refcount;
>> @@ -367,11 +366,15 @@ struct dpu_encoder_phys
> *dpu_encoder_phys_cmd_init(
>>  static inline enum dpu_3d_blend_mode
> dpu_encoder_helper_get_3d_blend_mode(
>>  		struct dpu_encoder_phys *phys_enc)
>>  {
>> +	struct dpu_crtc_state *dpu_cstate;
>> +
>>  	if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING)
>>  		return BLEND_3D_NONE;
>> 
>> +	dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
>> +
>>  	if (phys_enc->split_role == ENC_ROLE_SOLO &&
>> -	    phys_enc->topology_name == DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE)
>> +	    (dpu_cstate->num_mixers == 2))
>>  		return BLEND_3D_H_ROW_INT;
>> 
>>  	return BLEND_3D_NONE;
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
>> index a0b3744..88867c3 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
>> @@ -355,13 +355,14 @@ static void 
>> dpu_encoder_phys_vid_underrun_irq(void
> *arg, int irq_idx)
>> 
>>  static bool _dpu_encoder_phys_is_dual_ctl(struct dpu_encoder_phys
> *phys_enc)
>>  {
>> +	struct dpu_crtc_state *dpu_cstate;
>> +
>>  	if (!phys_enc)
>>  		return false;
>> 
>> -	if (phys_enc->topology_name == DPU_RM_TOPOLOGY_DUALPIPE)
>> -		return true;
>> +	dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
>> 
>> -	return false;
>> +	return (dpu_cstate->num_ctls > 1);
>>  }
>> 
>>  static bool dpu_encoder_phys_vid_needs_single_flush(
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>> index 13c0a36..1457ae5 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>> @@ -146,18 +146,6 @@ struct dpu_hw_mdp *dpu_rm_get_mdp(struct dpu_rm
> *rm)
>>  	return rm->hw_mdp;
>>  }
>> 
>> -enum dpu_rm_topology_name
>> -dpu_rm_get_topology_name(struct msm_display_topology topology)
>> -{
>> -	int i;
>> -
>> -	for (i = 0; i < DPU_RM_TOPOLOGY_MAX; i++)
>> -		if (RM_IS_TOPOLOGY_MATCH(g_top_table[i], topology))
>> -			return g_top_table[i].top_name;
>> -
>> -	return DPU_RM_TOPOLOGY_NONE;
>> -}
>> -
>>  void dpu_rm_init_hw_iter(
>>  		struct dpu_rm_hw_iter *iter,
>>  		uint32_t enc_id,
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>> index ffd1841..de52c03 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>> @@ -187,13 +187,4 @@ void dpu_rm_init_hw_iter(
>>   */
>>  int dpu_rm_check_property_topctl(uint64_t val);
>> 
>> -/**
>> - * dpu_rm_get_topology_name - returns the name of the the given
> topology
>> - *                            definition
>> - * @topology: topology definition
>> - * @Return: name of the topology
>> - */
>> -enum dpu_rm_topology_name
>> -dpu_rm_get_topology_name(struct msm_display_topology topology);
>> -
>>  #endif /* __DPU_RM_H__ */
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
> Forum,
>> a Linux Foundation Collaborative Project
>> 

-- 
Jeykumar S
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno