From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1EFCC433F5 for ; Thu, 21 Oct 2021 22:24:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B303D61251 for ; Thu, 21 Oct 2021 22:24:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231515AbhJUW0k (ORCPT ); Thu, 21 Oct 2021 18:26:40 -0400 Received: from m43-7.mailgun.net ([69.72.43.7]:13149 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229935AbhJUW0j (ORCPT ); Thu, 21 Oct 2021 18:26:39 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1634855063; h=Message-ID: References: In-Reply-To: Subject: Cc: To: From: Date: Content-Transfer-Encoding: Content-Type: MIME-Version: Sender; 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Thu, 21 Oct 2021 22:24:17 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Thu, 21 Oct 2021 15:24:17 -0700 From: abhinavk@codeaurora.org To: Dmitry Baryshkov Cc: Bjorn Andersson , Rob Clark , Sean Paul , Jonathan Marek , Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: Re: [Freedreno] [PATCH 02/11] drm/msm/dpu: remove pipe_qos_cfg from struct dpu_plane In-Reply-To: <20210930140002.308628-3-dmitry.baryshkov@linaro.org> References: <20210930140002.308628-1-dmitry.baryshkov@linaro.org> <20210930140002.308628-3-dmitry.baryshkov@linaro.org> Message-ID: X-Sender: abhinavk@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 2021-09-30 06:59, Dmitry Baryshkov wrote: > The pipe_qos_cfg is used only in _dpu_plane_set_qos_ctrl(), so remove > it > from the dpu_plane struct and allocate it on stack when necessary. > > Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 30 ++++++++++++----------- > 1 file changed, 16 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > index 5e0d06f26e53..88d726133b8b 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > @@ -105,7 +105,6 @@ struct dpu_plane { > > struct dpu_hw_pipe *pipe_hw; > struct dpu_hw_pipe_cfg pipe_cfg; > - struct dpu_hw_pipe_qos_cfg pipe_qos_cfg; > uint32_t color_fill; > bool is_error; > bool is_rt_pipe; > @@ -422,38 +421,41 @@ static void _dpu_plane_set_qos_ctrl(struct > drm_plane *plane, > bool enable, u32 flags) > { > struct dpu_plane *pdpu = to_dpu_plane(plane); > + struct dpu_hw_pipe_qos_cfg pipe_qos_cfg; > + > + memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg)); > > if (flags & DPU_PLANE_QOS_VBLANK_CTRL) { > - pdpu->pipe_qos_cfg.creq_vblank = pdpu->pipe_sblk->creq_vblank; > - pdpu->pipe_qos_cfg.danger_vblank = > + pipe_qos_cfg.creq_vblank = pdpu->pipe_sblk->creq_vblank; > + pipe_qos_cfg.danger_vblank = > pdpu->pipe_sblk->danger_vblank; > - pdpu->pipe_qos_cfg.vblank_en = enable; > + pipe_qos_cfg.vblank_en = enable; > } > > if (flags & DPU_PLANE_QOS_VBLANK_AMORTIZE) { > /* this feature overrules previous VBLANK_CTRL */ > - pdpu->pipe_qos_cfg.vblank_en = false; > - pdpu->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */ > + pipe_qos_cfg.vblank_en = false; > + pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */ > } > > if (flags & DPU_PLANE_QOS_PANIC_CTRL) > - pdpu->pipe_qos_cfg.danger_safe_en = enable; > + pipe_qos_cfg.danger_safe_en = enable; > > if (!pdpu->is_rt_pipe) { > - pdpu->pipe_qos_cfg.vblank_en = false; > - pdpu->pipe_qos_cfg.danger_safe_en = false; > + pipe_qos_cfg.vblank_en = false; > + pipe_qos_cfg.danger_safe_en = false; > } > > DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] > is_rt:%d\n", > pdpu->pipe - SSPP_VIG0, > - pdpu->pipe_qos_cfg.danger_safe_en, > - pdpu->pipe_qos_cfg.vblank_en, > - pdpu->pipe_qos_cfg.creq_vblank, > - pdpu->pipe_qos_cfg.danger_vblank, > + pipe_qos_cfg.danger_safe_en, > + pipe_qos_cfg.vblank_en, > + pipe_qos_cfg.creq_vblank, > + pipe_qos_cfg.danger_vblank, > pdpu->is_rt_pipe); > > pdpu->pipe_hw->ops.setup_qos_ctrl(pdpu->pipe_hw, > - &pdpu->pipe_qos_cfg); > + &pipe_qos_cfg); > } > > /**