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[212.182.62.129]) by smtp.gmail.com with ESMTPSA id n24-20020a05651203f800b00501c8959f6asm2954228lfq.98.2023.10.26.03.36.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 26 Oct 2023 03:36:53 -0700 (PDT) Message-ID: Date: Thu, 26 Oct 2023 12:36:49 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/5] arm64: dts: qcom: Add base SC8380XP dtsi and the QCP dts Content-Language: en-US To: Sibi Sankar , andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, catalin.marinas@arm.com, ulf.hansson@linaro.org Cc: agross@kernel.org, conor+dt@kernel.org, ayan.kumar.halder@amd.com, j@jannau.net, dmitry.baryshkov@linaro.org, nfraprado@collabora.com, m.szyprowski@samsung.com, u-kumar1@ti.com, peng.fan@nxp.com, lpieralisi@kernel.org, quic_rjendra@quicinc.com, abel.vesa@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, quic_tsoni@quicinc.com, neil.armstrong@linaro.org References: <20231025142427.2661-1-quic_sibis@quicinc.com> <20231025142427.2661-4-quic_sibis@quicinc.com> From: Konrad Dybcio In-Reply-To: <20231025142427.2661-4-quic_sibis@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 10/25/23 16:24, Sibi Sankar wrote: > From: Rajendra Nayak > > Add base dtsi and QCP board (Qualcomm Compute Platform) dts file for > SC8380XP SoC, describing the CPUs, GCC and RPMHCC clock controllers, > geni UART, interrupt controller, TLMM, reserved memory, interconnects, > SMMU and LLCC nodes. > > Co-developed-by: Abel Vesa > Signed-off-by: Abel Vesa > Signed-off-by: Rajendra Nayak > Co-developed-by: Sibi Sankar > Signed-off-by: Sibi Sankar > --- [...] > +&tlmm { > + gpio-reserved-ranges = <33 3>, <44 4>, <238 1>; It would be really cool if you added an explanation on why these GPIOs need to be reserved, especially since you can see what's connected on there on schematics. So, like: gpio-reserved-ranges = <33 3>, /* something */ <44 4>, /* something else (fp scanner?) <238 1>; /* UFS reset? */ [...] > + compatible = "qcom,oryon"; Again, this compatible won't fly unless all of these cores are totally identical and Oryon is only a name for this generation on this SoC (which I believe not to be the case). > + reg = <0x0 0x0>; > + enable-method = "psci"; > + next-level-cache = <&L1_0>; > + > + L1_0: l1-cache { > + compatible = "cache"; I'm not sure if L1 is supposed to be described in the DT, Krzysztof should know. > + next-level-cache = <&L2_0>; > + > + L2_0: l2-cache-0 { > + compatible = "cache"; cache-level? cache-unified? [...] > + memory@80000000 { > + device_type = "memory"; > + /* We expect the bootloader to fill in the size */ > + reg = <0 0x80000000 0 0x80000000>; That contradicts the comment you made above. Plus, 2 GiB seems a bit low for this SoC :D [...] > + gunyah_hyp_mem: gunyah-hyp-region@80000000 { you can probably strip the "-region" part, as this is implied by being a child of /reserved-memory > + pld_pep_mem: pld-pep-region@81f30000 { What's PLD? What's this region used for? PEP is a Windows invention. [...] > + av1_encoder_mem: av1-encoder-region@8e900000 { Is AV1enc hardware separate from iris? [...] > + gcc: clock-controller@100000 { > + compatible = "qcom,sc8380xp-gcc"; > + reg = <0 0x100000 0 0x200000>; The address part of reg should be padded to 8 hex digits. > + > + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, QCOM_ICC_TAG_ALWAYS would be nicer than 0 (see sa8775p) [...] > + > + interrupts = , One space after and before '=' Konrad