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Tue, 25 Mar 2025 15:12:35 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 52PFCY8M032085 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Mar 2025 15:12:35 GMT Received: from [10.253.12.41] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 25 Mar 2025 08:12:30 -0700 Message-ID: Date: Tue, 25 Mar 2025 23:12:28 +0800 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/4] clk: qcom: cmnpll: Add IPQ5424 SoC support To: Stephen Boyd , Bjorn Andersson , Conor Dooley , Konrad Dybcio , Krzysztof Kozlowski , Michael Turquette , Rob Herring CC: , , , , , , , , References: <20250321-qcom_ipq5424_cmnpll-v1-0-3ea8e5262da4@quicinc.com> <20250321-qcom_ipq5424_cmnpll-v1-2-3ea8e5262da4@quicinc.com> Content-Language: en-US From: Jie Luo In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=fNc53Yae c=1 sm=1 tr=0 ts=67e2c7e4 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=Ibpr2pAS98eo1bZLyFsA:9 a=QEXdDO2ut3YA:10 a=RVmHIydaz68A:10 X-Proofpoint-ORIG-GUID: NjUsQ-yxK3Ygpo4SOD3WJEhK4Jdx_Hvn X-Proofpoint-GUID: NjUsQ-yxK3Ygpo4SOD3WJEhK4Jdx_Hvn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-25_06,2025-03-25_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 mlxlogscore=999 priorityscore=1501 mlxscore=0 adultscore=0 spamscore=0 bulkscore=0 suspectscore=0 phishscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503250107 On 3/25/2025 7:42 AM, Stephen Boyd wrote: > Quoting Luo Jie (2025-03-21 05:49:53) >> diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c >> index 432d4c4b7aa6..ce5e83124c6d 100644 >> --- a/drivers/clk/qcom/ipq-cmn-pll.c >> +++ b/drivers/clk/qcom/ipq-cmn-pll.c >> @@ -1,6 +1,6 @@ >> // SPDX-License-Identifier: GPL-2.0-only >> /* >> - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. >> + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. >> */ >> >> /* >> @@ -16,6 +16,10 @@ >> * are supplied to GCC (24 MHZ as XO and 32 KHZ as sleep clock), and to PCS >> * with 31.25 MHZ. >> * >> + * On the IPQ5424 SoC, there is an output clock from CMN PLL to PPE at 375 MHZ, >> + * and an output clock to NSS at 300 MHZ. The other output clocks from CMN PLL >> + * on IPQ5424 are the same as IPQ9574. >> + * >> * +---------+ >> * | GCC | >> * +--+---+--+ >> @@ -115,6 +119,20 @@ static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] = { >> CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), >> CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), >> CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), >> + { /* Sentinel */ }, > > Nitpick: Drop the comma here so nothing can come after the sentinel. Understand, I will remove it. > >> +}; >> + >> +static const struct cmn_pll_fixed_output_clk ipq5424_output_clks[] = { >> + CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL), >> + CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), >> + CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), >> + CLK_PLL_OUTPUT(NSS_300MHZ_CLK, "nss-300mhz", 300000000UL), >> + CLK_PLL_OUTPUT(PPE_375MHZ_CLK, "ppe-375mhz", 375000000UL), >> + CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL), >> + CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), >> + CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), >> + CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), >> + { /* Sentinel */ }, > > Nitpick: Drop the comma here so nothing can come after the sentinel. > OK. >> }; >> >> /* >