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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id b24-20020ac247f8000000b004edd4d1e55dsm697027lfp.284.2023.04.21.16.09.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 21 Apr 2023 16:09:16 -0700 (PDT) Message-ID: Date: Sat, 22 Apr 2023 02:09:15 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [PATCH 2/2] drm/msm/dpu: remove GC related code from dpu catalog Content-Language: en-GB To: Abhinav Kumar , freedreno@lists.freedesktop.org, Rob Clark , Sean Paul , David Airlie , Daniel Vetter Cc: dri-devel@lists.freedesktop.org, quic_jesszhan@quicinc.com, marijn.suijten@somainline.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230421224721.12738-1-quic_abhinavk@quicinc.com> <20230421224721.12738-2-quic_abhinavk@quicinc.com> From: Dmitry Baryshkov In-Reply-To: <20230421224721.12738-2-quic_abhinavk@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 22/04/2023 01:47, Abhinav Kumar wrote: > Since Gamma Correction (GC) block is currently unused, drop > related code from the dpu hardware catalog otherwise this > becomes a burden to carry across chipsets in the catalog. > > Signed-off-by: Abhinav Kumar > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 +--- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 6 ------ > 2 files changed, 1 insertion(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 03f162af1a50..badfc3680485 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -91,7 +91,7 @@ > > #define MERGE_3D_SM8150_MASK (0) > > -#define DSPP_MSM8998_MASK BIT(DPU_DSPP_PCC) | BIT(DPU_DSPP_GC) > +#define DSPP_MSM8998_MASK BIT(DPU_DSPP_PCC) > > #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC) At this point we can merge these two masks. Could you please extend this for v2 with the following patches: - merge of two DSPP_foo_MASKs - dropping of DPU_DSPP_IGC? For this patch: Reviewed-by: Dmitry Baryshkov > > @@ -449,8 +449,6 @@ static const struct dpu_lm_sub_blks qcm2290_lm_sblk = { > static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = { > .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700, > .len = 0x90, .version = 0x10007}, > - .gc = { .id = DPU_DSPP_GC, .base = 0x17c0, > - .len = 0x90, .version = 0x10007}, > }; > > static const struct dpu_dspp_sub_blks sc7180_dspp_sblk = { > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index 71584cd56fd7..e0dcef04bc61 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -127,12 +127,10 @@ enum { > /** > * DSPP sub-blocks > * @DPU_DSPP_PCC Panel color correction block > - * @DPU_DSPP_GC Gamma correction block > * @DPU_DSPP_IGC Inverse gamma correction block > */ > enum { > DPU_DSPP_PCC = 0x1, > - DPU_DSPP_GC, > DPU_DSPP_IGC, > DPU_DSPP_MAX > }; > @@ -433,22 +431,18 @@ struct dpu_sspp_sub_blks { > * @maxwidth: Max pixel width supported by this mixer > * @maxblendstages: Max number of blend-stages supported > * @blendstage_base: Blend-stage register base offset > - * @gc: gamma correction block > */ > struct dpu_lm_sub_blks { > u32 maxwidth; > u32 maxblendstages; > u32 blendstage_base[MAX_BLOCKS]; > - struct dpu_pp_blk gc; > }; > > /** > * struct dpu_dspp_sub_blks: Information of DSPP block > - * @gc : gamma correction block > * @pcc: pixel color correction block > */ > struct dpu_dspp_sub_blks { > - struct dpu_pp_blk gc; > struct dpu_pp_blk pcc; > }; > -- With best wishes Dmitry