From: Harshal Dev <harshal.dev@oss.qualcomm.com>
To: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Cc: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Val Packett <val@packett.cool>,
Stephan Gerhold <stephan.gerhold@linaro.org>,
Abel Vesa <abel.vesa@oss.qualcomm.com>,
Udit Tiwari <quic_utiwari@quicinc.com>,
Neeraj Soni <quic_neersoni@quicinc.com>
Subject: Re: [PATCH v4] arm64: dts: qcom: x1e80100: Add crypto engine
Date: Wed, 10 Dec 2025 10:43:59 +0530 [thread overview]
Message-ID: <f41c3d9e-2597-4c33-96c1-0eeba41dc803@oss.qualcomm.com> (raw)
In-Reply-To: <vvbtsf4qw7c7ymshxjdxlprtw3s3fctldvpw6zw4h5ny43wmju@ln7ecfh7y34j>
On 12/9/2025 1:09 PM, Dmitry Baryshkov wrote:
> On Tue, Dec 09, 2025 at 12:57:29PM +0530, Harshal Dev wrote:
>> Hi,
>>
>> On 12/8/2025 9:26 PM, Konrad Dybcio wrote:
>>> On 12/8/25 1:32 PM, Harshal Dev wrote:
>>>> On X Elite, there is a crypto engine IP block similar to ones found on
>>>> SM8x50 platforms.
>>>>
>>>> Describe the crypto engine and its BAM.
>>>>
>>>> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
>>>> ---
>>>> The dt-binding schema update for the x1e80100 compatible is here
>>>> (already merged):
>>>>
>>>> https://lore.kernel.org/all/20250213-dt-bindings-qcom-qce-x1e80100-v1-1-d17ef73a1c12@linaro.org/
>>>> ---
>>>
>>>
>>>> + cryptobam: dma-controller@1dc4000 {
>>>> + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
>>>> + reg = <0x0 0x01dc4000 0x0 0x28000>;
>>>> + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
>>>> + #dma-cells = <1>;
>>>> + iommus = <&apps_smmu 0x480 0x0>,
>>>> + <&apps_smmu 0x481 0x0>;
>>>> + qcom,ee = <0>;
>>>> + qcom,controlled-remotely;
>>>> + num-channels = <20>;
>>>> + qcom,num-ees = <4>;
>>>> + };
>>>> +
>>>> + crypto: crypto@1dfa000 {
>>>> + compatible = "qcom,x1e80100-qce", "qcom,sm8150-qce", "qcom,qce";
>>>> + reg = <0x0 0x01dfa000 0x0 0x6000>;
>>>> + dmas = <&cryptobam 4>, <&cryptobam 5>;
>>>> + dma-names = "rx",
>>>> + "tx";
>>>> + iommus = <&apps_smmu 0x480 0x0>,
>>>> + <&apps_smmu 0x481 0x0>;
>>>> + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
>>>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
>>>> + interconnect-names = "memory";
>>>> + };
>>>> +
>>>> cnoc_main: interconnect@1500000 {
>>>
>>> Right as I hit enter for the rb message, I noticed the nodes you're
>>> adding are not sorted - please sort them wrt the unit address (@foo)
>>> and retain my tag then
>>>
>>
>> Not sure if I understand you Konrad.. I believe the nodes are already sorted
>> since address (crypto) @1dfa000 > address (cryptobam) @1dc4000? Do let me know what
>> I'm missing.
>
> 0x01dfa000 > 0x1500000, so no, your nodes are not properly sorted.
>
Thank you for spotting this folks. I realize that the sorting was correct in v1 of the patch
from Abel. I will revert back to that.
Thanks!
Harshal
>>
>> Thanks,
>> Harshal
>>
>>> Konrad
>>
>
next prev parent reply other threads:[~2025-12-10 5:14 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-08 12:32 [PATCH v4] arm64: dts: qcom: x1e80100: Add crypto engine Harshal Dev
2025-12-08 15:55 ` Konrad Dybcio
2025-12-08 15:56 ` Konrad Dybcio
2025-12-09 7:27 ` Harshal Dev
2025-12-09 7:39 ` Dmitry Baryshkov
2025-12-10 5:13 ` Harshal Dev [this message]
2025-12-09 6:41 ` Wenjia Zhang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=f41c3d9e-2597-4c33-96c1-0eeba41dc803@oss.qualcomm.com \
--to=harshal.dev@oss.qualcomm.com \
--cc=abel.vesa@oss.qualcomm.com \
--cc=andersson@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=dmitry.baryshkov@oss.qualcomm.com \
--cc=konrad.dybcio@oss.qualcomm.com \
--cc=konradybcio@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=quic_neersoni@quicinc.com \
--cc=quic_utiwari@quicinc.com \
--cc=robh@kernel.org \
--cc=stephan.gerhold@linaro.org \
--cc=val@packett.cool \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox