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Wed, 17 Sep 2025 12:47:43 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFjiteAoD9cK/bN/ETaRodNHrRIWIEDt3HvpK3XaXv5ZIiOHuqKosTaZcxNGnpqJN5t22Zbpg== X-Received: by 2002:a17:90b:5788:b0:32d:dffc:7ad6 with SMTP id 98e67ed59e1d1-32ee3f8c588mr4286845a91.33.1758138462681; Wed, 17 Sep 2025 12:47:42 -0700 (PDT) Received: from [10.216.40.15] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-77cfc24b4f6sm215021b3a.37.2025.09.17.12.47.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 17 Sep 2025 12:47:42 -0700 (PDT) Message-ID: Date: Thu, 18 Sep 2025 01:17:30 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V7 4/5] iio: adc: Add support for QCOM PMIC5 Gen3 ADC To: Jonathan Cameron Cc: robh@kernel.org, krzysztof.kozlowski@linaro.org, krzk+dt@kernel.org, conor+dt@kernel.org, agross@kernel.org, andersson@kernel.org, lumag@kernel.org, dmitry.baryshkov@oss.qualcomm.com, konradybcio@kernel.org, daniel.lezcano@linaro.org, sboyd@kernel.org, amitk@kernel.org, thara.gopinath@gmail.com, lee@kernel.org, rafael@kernel.org, subbaraman.narayanamurthy@oss.qualcomm.com, david.collins@oss.qualcomm.com, anjelique.melendez@oss.qualcomm.com, kamal.wadhwa@oss.qualcomm.com, rui.zhang@intel.com, lukasz.luba@arm.com, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, cros-qcom-dts-watchers@chromium.org, quic_kotarake@quicinc.com, neil.armstrong@linaro.org, stephan.gerhold@linaro.org References: <20250826083657.4005727-1-jishnu.prakash@oss.qualcomm.com> <20250826083657.4005727-5-jishnu.prakash@oss.qualcomm.com> <20250830184233.7ddf6ae8@jic23-huawei> Content-Language: en-US From: Jishnu Prakash In-Reply-To: <20250830184233.7ddf6ae8@jic23-huawei> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=YfO95xRf c=1 sm=1 tr=0 ts=68cb1060 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=UEldCo81gXLG25mkEUsA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-GUID: vCqyMQeXjJFL9CPhnPfnsLEtVDIWRmSD X-Proofpoint-ORIG-GUID: vCqyMQeXjJFL9CPhnPfnsLEtVDIWRmSD X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTE3MDE4MiBTYWx0ZWRfX3oUMqE6WX5BO A3KALrXunnbKX0pvNiHQR1ccM37j6zAEGU2JaDfpqpFZ0FH4Gj57JkhQ1kH624bDmRcOycg9APo TKPOpU+NP4dYThp5bsOTHjVauNg2/s4dnmp+BL2oYhYhhO03hKMi0W5cyVuRJ7CpMlzO/jBrX/a NE+VUgh9T3ovsuD4qG+EY/B0BncIomcWzkyexHjGmmZG0CzXxwwRu+fk+7B2WxoCuzl0kjAuVvc ah0wLRCEWe1r+UiiX4iTdO0zYqKdK8pmzDro/fOVo1nT3gP7739NFgEsu0sVacRRwmwEY5V2C52 f/iTXB+wF1i0LrxgAACvnt6VCSqWs5MXVOdXQPejcNiJzqlMwdjUMGoN2FY87UYzqo/unU4oqw8 vSLaBDx3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-17_01,2025-09-17_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 spamscore=0 phishscore=0 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509170182 Hi Jonathan, On 8/30/2025 11:12 PM, Jonathan Cameron wrote: > On Tue, 26 Aug 2025 14:06:56 +0530 > Jishnu Prakash wrote: > >> The ADC architecture on PMIC5 Gen3 is similar to that on PMIC5 Gen2, >> with all SW communication to ADC going through PMK8550 which >> communicates with other PMICs through PBS. >> >> One major difference is that the register interface used here is that >> of an SDAM (Shared Direct Access Memory) peripheral present on PMK8550. >> There may be more than one SDAM used for ADC5 Gen3 and each has eight >> channels, which may be used for either immediate reads (same functionality >> as previous PMIC5 and PMIC5 Gen2 ADC peripherals) or recurring measurements >> (same as ADC_TM functionality). >> >> By convention, we reserve the first channel of the first SDAM for all >> immediate reads and use the remaining channels across all SDAMs for >> ADC_TM monitoring functionality. >> >> Add support for PMIC5 Gen3 ADC driver for immediate read functionality. >> ADC_TM is implemented as an auxiliary thermal driver under this ADC >> driver. >> >> Signed-off-by: Jishnu Prakash > > Hi Jishnu, > > A few additional comments from a fresh read through. > > Thanks, > > Jonathan > .... >> + >> +static int adc5_gen3_get_fw_channel_data(struct adc5_chip *adc, >> + struct adc5_channel_prop *prop, >> + struct fwnode_handle *fwnode) >> +{ >> + const char *name = fwnode_get_name(fwnode); >> + const struct adc5_data *data = adc->data; >> + u32 chan, value, varr[2], sid = 0; > > Why initialize sid? I think this is not needed, I'll remove it. I'll also address all your other comments in the next patch series. Thanks, Jishnu > >> + struct device *dev = adc->dev; >> + const char *channel_name; >> + int ret; >> + >> + ret = fwnode_property_read_u32(fwnode, "reg", &chan); >> + if (ret < 0) >> + return dev_err_probe(dev, ret, "invalid channel number %s\n", >> + name); >> + >> + /* >> + * Value read from "reg" is virtual channel number >> + * virtual channel number = sid << 8 | channel number >> + */ >> + sid = FIELD_GET(ADC5_GEN3_VIRTUAL_SID_MASK, chan); >> + chan = FIELD_GET(ADC5_GEN3_CHANNEL_MASK, chan); > >> + return 0; >> +} >