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Mon, 24 Mar 2025 06:51:23 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 52O6pNJ6004644 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 24 Mar 2025 06:51:23 GMT Received: from [10.233.19.224] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 23 Mar 2025 23:51:18 -0700 Message-ID: Date: Mon, 24 Mar 2025 14:51:16 +0800 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 2/3] arm64: dts: qcom: x1e80100: add bus topology for PCIe domain 3 To: Bryan O'Donoghue , , , , , , , , , , , , , References: <20250320055502.274849-1-quic_wenbyao@quicinc.com> <20250320055502.274849-3-quic_wenbyao@quicinc.com> <7dc8700f-0d53-45f5-bfff-2bec71c7053e@linaro.org> Content-Language: en-US From: "Wenbin Yao (Consultant)" In-Reply-To: <7dc8700f-0d53-45f5-bfff-2bec71c7053e@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 4bZ011oTBBWHLyE3D42KmUuTLccUKLHG X-Proofpoint-ORIG-GUID: 4bZ011oTBBWHLyE3D42KmUuTLccUKLHG X-Authority-Analysis: v=2.4 cv=JvPxrN4C c=1 sm=1 tr=0 ts=67e100eb cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=Upqwyp-cVDBhw83K_eoA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-24_03,2025-03-21_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 malwarescore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 suspectscore=0 phishscore=0 impostorscore=0 adultscore=0 clxscore=1011 mlxscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503240049 On 3/21/2025 6:06 AM, Bryan O'Donoghue wrote: > On 20/03/2025 05:55, Wenbin Yao wrote: >> From: Qiang Yu >> >> Add pcie3port node to represent the PCIe bridge of PCIe3 so that PCI >> slot >> voltage rails can be described under this node in the board's dts. >> >> Signed-off-by: Qiang Yu >> Signed-off-by: Wenbin Yao >> --- >>   arch/arm64/boot/dts/qcom/x1e80100.dtsi | 10 ++++++++++ >>   1 file changed, 10 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi >> b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >> index 46b79fce9..32e8d400a 100644 >> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi >> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >> @@ -3287,6 +3287,16 @@ opp-128000000 { >>                       opp-peak-kBps = <15753000 1>; >>                   }; >>               }; >> +            pcie3port: pcie@0 { > > Missing newline, please check your dtb checks. Will fix in the next version. > > >> +                device_type = "pci"; >> +                compatible = "pciclass,0604"; >> +                reg = <0x0 0x0 0x0 0x0 0x0>; >> +                bus-range = <0x01 0xff>; >> + >> +                #address-cells = <3>; >> +                #size-cells = <2>; >> +                ranges; >> +            }; >>           }; > > Why is pice3port the only port to be enabled ? > > What about the other ports ? Only PCIe3 requires PCI slot power driver to power on its slots, other ports don‘t need it. >>           pcie3_phy: phy@1be0000 { >> -- >> 2.34.1 >> >> > > --- > bod -- With best wishes Wenbin