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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b65eb03649dsm1041530466b.50.2025.10.21.03.39.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Oct 2025 03:39:38 -0700 (PDT) Message-ID: Date: Tue, 21 Oct 2025 12:39:37 +0200 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] arm64: dts: qcom: sm8550: Additionally manage MXC power domain in camcc To: Luca Weiss , Taniya Das , Dmitry Baryshkov , Vladimir Zapolskiy Cc: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jagadeesh Kona , Bryan O'Donoghue , Michael Turquette , Stephen Boyd , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org References: <20250303225521.1780611-1-vladimir.zapolskiy@linaro.org> <20250303225521.1780611-3-vladimir.zapolskiy@linaro.org> <3210a484-b9c3-4399-bee1-9f5bbc90034c@linaro.org> <85bf3468-24bf-4f14-afcd-28878ad84dc9@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: Bm6SeoW0mnV5bZhH0aP4PPInDzQyCZIY X-Proofpoint-GUID: Bm6SeoW0mnV5bZhH0aP4PPInDzQyCZIY X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE5MDA5MCBTYWx0ZWRfX4JQvQ/uAZhkn sSobKhR8xKUtmU5YJ+N1jWRDeWUEtaN8dIAi6XNXl5l++5ZkHoHrc+JpMz5AguA/fAc820uwKP8 KItLARGWMfy9G1JuLKDgVou+mu2A+6zps5irPk7KYh5WcSgQCcG10aplJ7btCItv6ak3zwRCyy2 EcEOYG07q8wDWTxRgKNel2Y9H8aABmw8trKmNK36oaAaR3jonvCKwj2EHcT/DyRCbuRis6xFjWw XijuGn7JI3/3MOhc7eY+hJJfw7jPyqLDhvjzRxiXTZO0jrUejUq38F4tgN69dDTB/+HHzOMRuyT syVkJ/rbNSeryqgTJNdjZAVc0MKL8QsA9RVWF9A2QG/NFUNeW0Z4BaIZz8CgBPvFlpL2TuGx0sI vqxzjD6e2gsgWL2XM+mkkZcq7V8qqg== X-Authority-Analysis: v=2.4 cv=V5NwEOni c=1 sm=1 tr=0 ts=68f762ed cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=z5B4IXqlO_MRCTr_IEYA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-21_01,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 suspectscore=0 clxscore=1015 phishscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510190090 On 10/21/25 12:36 PM, Luca Weiss wrote: > On Mon Oct 20, 2025 at 2:21 PM CEST, Konrad Dybcio wrote: >> On 10/17/25 4:05 PM, Luca Weiss wrote: >>> Hi Taniya, >>> >>> On Thu Mar 13, 2025 at 12:57 PM CET, Taniya Das wrote: >>>> >>>> >>>> On 3/13/2025 1:22 PM, Luca Weiss wrote: >>>>> Hi Taniya, >>>>> >>>>> On Thu Mar 13, 2025 at 5:39 AM CET, Taniya Das wrote: >>>>>> >>>>>> >>>>>> On 3/4/2025 2:10 PM, Dmitry Baryshkov wrote: >>>>>>> On Tue, 4 Mar 2025 at 09:37, Vladimir Zapolskiy >>>>>>> wrote: >>>>>>>> >>>>>>>> On 3/4/25 01:53, Dmitry Baryshkov wrote: >>>>>>>>> On Tue, Mar 04, 2025 at 12:55:21AM +0200, Vladimir Zapolskiy wrote: >>>>>>>>>> SM8550 Camera Clock Controller shall enable both MXC and MMCX power >>>>>>>>>> domains. >>>>>>>>> >>>>>>>>> Are those really required to access the registers of the cammcc? Or is >>>>>>>>> one of those (MXC?) required to setup PLLs? Also, is this applicable >>>>>>>>> only to sm8550 or to other similar clock controllers? >>>>>>>> >>>>>>>> Due to the described problem I experience a fatal CPU stall on SM8550-QRD, >>>>>>>> not on any SM8450 or SM8650 powered board for instance, however it does >>>>>>>> not exclude an option that the problem has to be fixed for other clock >>>>>>>> controllers, but it's Qualcomm to confirm any other touched platforms, >>>>>>> >>>>>>> Please work with Taniya to identify used power domains. >>>>>>> >>>>>> >>>>>> CAMCC requires both MMCX and MXC to be functional. >>>>> >>>>> Could you check whether any clock controllers on SM6350/SM7225 (Bitra) >>>>> need multiple power domains, or in general which clock controller uses >>>>> which power domain. >>>>> >>>>> That SoC has camcc, dispcc, gcc, gpucc, npucc and videocc. >>>>> >>>>> That'd be highly appreciated since I've been hitting weird issues there >>>>> that could be explained by some missing power domains. >>>>> >>>> >>>> Hi Luca, >>>> >>>> The targets you mentioned does not have any have multiple rail >>>> dependency, but could you share the weird issues with respect to clock >>>> controller I can take a look. >>> >>> Coming back to this, I've taken a shot at camera on SM6350 (Fairphone 4) >>> again, but again hitting some clock issues. >>> >>> For reference, I am testing with following change: >>> https://lore.kernel.org/linux-arm-msm/20250911011218.861322-3-vladimir.zapolskiy@linaro.org/ >>> >>> Trying to enable CAMCC_MCLK1_CLK - wired up to the IMX576 camera sensor >>> on this phone - results in following error. >>> >>> [ 3.140232] ------------[ cut here ]------------ >>> [ 3.141264] camcc_mclk1_clk status stuck at 'off' >>> [ 3.141276] WARNING: CPU: 6 PID: 12 at drivers/clk/qcom/clk-branch.c:87 clk_branch_toggle+0x170/0x190 >>> >>> Checking the driver against downstream driver, it looks like the RCGs >>> should be using clk_rcg2_shared_ops because of enable_safe_config in >>> downstream, but changing that doesn't really improve the situation, but >>> it does change the error message to this: >>> >>> [ 2.933254] ------------[ cut here ]------------ >>> [ 2.933961] camcc_mclk1_clk_src: rcg didn't update its configuration. >>> [ 2.933970] WARNING: CPU: 7 PID: 12 at drivers/clk/qcom/clk-rcg2.c:136 update_config+0xd4/0xe4 >>> >>> I've also noticed that some camcc drivers take in GCC_CAMERA_AHB_CLK as >>> iface clk, could something like this be missing on sm6350? >>> >>> I'd appreciate any help or tips for resolving this. >> >> Is CAMCC_PLL2 online? > > I'd assume so given nothing in dmesg is complaining about that? > > But not sure how to check. Debugcc can't do PLLs, right? The PLLs have a .is_enabled, so you can take a look in debugfs > In any case adding CLK_IS_CRITICAL to the camcc_pll2 doesn't change > anything. Was worth a shot :( Konrad