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Mon, 24 Mar 2025 16:44:11 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 52OGiAYl027527 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 24 Mar 2025 16:44:10 GMT Received: from [10.216.17.237] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 24 Mar 2025 09:44:06 -0700 Message-ID: Date: Mon, 24 Mar 2025 22:14:03 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1] arm64: dts: qcom: sa8775p: Add default pin configurations for QUP SEs To: Bjorn Andersson CC: , , , , , , , , References: <20250225154136.3052757-1-quic_vdadhani@quicinc.com> Content-Language: en-US From: Viken Dadhaniya In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ikxVXsEEZAd1-hjUiVAsxZMkQpXz-xsw X-Proofpoint-ORIG-GUID: ikxVXsEEZAd1-hjUiVAsxZMkQpXz-xsw X-Authority-Analysis: v=2.4 cv=CPoqXQrD c=1 sm=1 tr=0 ts=67e18bdb cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=Fu_YwIdgIx9_JamtqNsA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-24_04,2025-03-21_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxlogscore=988 spamscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 phishscore=0 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503240120 On 3/4/2025 10:05 AM, Bjorn Andersson wrote: > On Tue, Feb 25, 2025 at 09:11:36PM +0530, Viken Dadhaniya wrote: >> Default pinctrl configurations for all QUP (Qualcomm Universal Peripheral) >> Serial Engines (SEs) are missing in the SoC device tree. These >> configurations are required by client teams when enabling any SEs as I2C, >> SPI, or Serial protocols. >> >> Add default pin configurations for Serial Engines (SEs) for all supported >> protocols, including I2C, SPI, and UART, to the sa8775p device tree. This >> change facilitates slave device driver clients to enable usecase with >> minimal modifications. >> >> Additionally, move default pin configurations from target-specific files to >> the SoC device tree file, as all possible pin configurations are now >> comprehensively included in the SoC device tree, similar to other SoCs. >> >> Signed-off-by: Viken Dadhaniya >> --- >> arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 88 -- >> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 908 +++++++++++++++++++++ >> 2 files changed, 908 insertions(+), 88 deletions(-) >> > [..] >> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > [..] >> + qup_i2c0_default: qup-i2c0-state { >> + pins = "gpio20", "gpio21"; >> + function = "qup0_se0"; >> + drive-strength = <2>; >> + bias-pull-up; > > Look at other examples, such as sc7280.dtsi, and you will see that > drive-strength and bias are considered board-specific properties and > should thereby not go in the soc.dtsi file. > Removed drive-strength and bias in v2. > Thanks, > Bjorn