Re: [PATCH v2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: disable WCN6750 and WPSS

[Hangtian Zhu <hangtian.zhu@oss.qualcomm.com>]

On 3/12/2026 11:04, Dmitry Baryshkov wrote:
> On Wed, Mar 11, 2026 at 03:06:08PM +0800, Hangtian Zhu wrote:
>>
>>
>> On 3/11/2026 12:34, Dmitry Baryshkov wrote:
>>> On Wed, Mar 11, 2026 at 11:11:45AM +0800, Hangtian Zhu wrote:
>>>> From: Hangtian Zhu <hangtian@oss.qualcomm.com>
>>>>
>>>> Disable WCN6750 and WPSS on industrial mezzanine. On RB3 Gen2 industrial
>>>
>>> You can't disable these devices on the mezzanine, they are not a part of
>>> it.
>>>
>>>> mezzanine platform, pcie0 lines are moved from WCN6750 to QPS615 pcie
>>>
>>> PCIe0. How re they moved? What triggers the move?
>> Please refer to: https://lore.kernel.org/all/20260305-industrial-mezzanine-pcie-v4-0-1f2c9d1344d7@oss.qualcomm.com/
>> On RB3 Gen2 industrial mezzanine, WCN6750 is not connected, instead TC9563 PCIe bridge is connected to PCIe0.
> 
> THis doesn't answer the question, what triggers the move? Is it done
> automatically? Is there a pin that is sourced by the carrier board?
> Is there something else?
It's the hardware design itself. Industrial mezzanine (should be called 'kit') is not a plugin device on top of core kit, but a non‑modular integrated device.
Hardware redesigned QCS6490 SOM and disconnected WCN6750 from PCIe0 for this device, PCIe0 connects TC9563 PCIe bridge.

> 
>>
>>>
>>>> bridge. Hence disable WPSS and WCN6750 nodes for industrial mezzanine
>>>> platform.
>>>>
>>>> Depends-on: https://lore.kernel.org/all/20260305-industrial-mezzanine-pcie-v4-2-1f2c9d1344d7@oss.qualcomm.com/
>>>
>>> NAK. Don't invent non-standard tags.
>>>
>>>>
>>>> Signed-off-by: Hangtian Zhu <hangtian@oss.qualcomm.com>
>>>> ---
>>>>  .../dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso    | 8 ++++++++
>>>>  1 file changed, 8 insertions(+)
>>>>
>>>
>>
>