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Thu, 05 Feb 2026 20:58:21 -0800 (PST) X-Received: by 2002:a17:902:e54a:b0:2a9:320a:eca with SMTP id d9443c01a7336-2a951636d79mr15637595ad.22.1770353900783; Thu, 05 Feb 2026 20:58:20 -0800 (PST) Received: from [10.217.216.195] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a951c71edasm10164305ad.22.2026.02.05.20.58.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Feb 2026 20:58:20 -0800 (PST) Message-ID: Date: Fri, 6 Feb 2026 10:28:15 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/3] dt-bindings: interconnect: qcom,qcs615-rpmh: add clocks property to enable QoS To: Dmitry Baryshkov Cc: Konrad Dybcio , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Raviteja Laggyshetty , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mike Tipton References: <20260202070534.1281652-1-odelu.kukatla@oss.qualcomm.com> <20260202070534.1281652-2-odelu.kukatla@oss.qualcomm.com> <95d42fb7-2365-46a0-a995-c9cc51b17424@oss.qualcomm.com> Content-Language: en-US From: Odelu Kukatla In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjA2MDAyOSBTYWx0ZWRfX327HYOK9KzbX vLhi+YDUu2YKT/7WH3suGhurhzfNxf8u+nKBf/6uXoLKG2wCNM3saLEsFagPvcdmkzTAYFVx3Aa HCiUw2BUkCofYpLLgB97SClxsjbN7vaP6DZ9QbJjLnRkubJkYZ/0IlpMfij+HA3oorGgqXoDtA+ eCFlKsGtXlGsWpZYsej/7SUVLDCwBW39E98vZbTgMcbO1EDjQrr5Kd1Zrv3MTHWJ4Ggs28ehq8Z JaE531pH+3/oRrrpbOYUl3J2cUH2ABn0n3VYacqIlEBMxofC3nLB7mfGaTA8Sruq8oRTqwO81uQ OEyAjHYWhBNZzG2F62nkiYT701YpEh1Ft18fGgzv7BCill25q5XwJ5jdtOQ/3HPPcoAbBZDtpRo Dr0NVssihcScYxe61ueD5REoAt225u8vChVmWe/GoM2/gCBYsaPHqM8Qn3tDVaur5CRQ/VWLLNm NlmvHFlsiaOnT54i1cw== X-Proofpoint-ORIG-GUID: 4OPAE5pijOKeorWL8fY9cDM5uW_HgJnt X-Proofpoint-GUID: 4OPAE5pijOKeorWL8fY9cDM5uW_HgJnt X-Authority-Analysis: v=2.4 cv=Z6zh3XRA c=1 sm=1 tr=0 ts=698574ed cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=8fnAZSNZBFF80Bt1M-IA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-06_01,2026-02-05_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602060029 On 2/5/2026 3:59 PM, Dmitry Baryshkov wrote: > On Thu, Feb 05, 2026 at 03:10:31PM +0530, Odelu Kukatla wrote: >> >> >> On 2/5/2026 2:31 PM, Konrad Dybcio wrote: >>> On 2/5/26 7:06 AM, Odelu Kukatla wrote: >>>> >>>> >>>> On 2/2/2026 4:33 PM, Konrad Dybcio wrote: >>>>> On 2/2/26 8:05 AM, Odelu Kukatla wrote: >>>>>> Aggre1-noc interconnect node on QCS615 has QoS registers located >>>>>> inside a block whose interface is clock-gated. For that node, >>>>>> driver must enable the corresponding clock(s) before accessing >>>>>> the registers. Add the 'clocks' property so the driver can obtain >>>>>> and enable the required clock(s). >>>>>> >>>>>> Only interconnects that have clock‑gated QoS register interface >>>>>> use this property; it is not applicable to all interconnect nodes. >>>>>> >>>>>> Signed-off-by: Odelu Kukatla >>>>>> --- >>> >>> [...] >>> >>>>>> + - if: >>>>>> + properties: >>>>>> + compatible: >>>>>> + contains: >>>>>> + enum: >>>>>> + - qcom,qcs615-aggre1-noc >>>>>> + then: >>>>>> + properties: >>>>>> + clocks: >>>>>> + items: >>>>>> + - description: aggre UFS PHY AXI clock >>>>>> + - description: aggre USB2 SEC AXI clock >>>>>> + - description: aggre USB3 PRIM AXI clock >>>>> >>>>> Should we also include the IPA clock here? >>>>> >>>> >>>> Thanks for the review! >>>> >>>> For QCS615, the IPA clock is already enabled by the bootloader (xBL) and >>>> kept on during the boot‑up stage. Because of this, we do not need to >>>> explicitly enable the IPA clock in the interconnect driver when >>>> accessing the QoS registers. >>> >>> Would we need to re-enable it to re-program the hardware if say the >>> icc module is loaded after unused clk cleanup or after a cx collapse? >>> >> >> IPA clock is not managed by GCC clock controller driver, so >> clk_disable_unused does not disable it. > > The clk_disable_unused is not limited to the GCC. The clock is managed > by the clk-rpmh, so clk_disable_unused applies to it too. > clk_disable_unused()/clk_disable_unused_subtree() does not disable RPMh managed clocks, so it does not apply to IPA clock. >> As a result, the icc provider >> does not need to re enable an IPA clock for QoS access after unused clk >> cleanup. And QCS615 does *not* support Cx collapse. > > Does lack of CX collapse apply to SM6150? > SM6150, QCS615, and Talos are all names referring to the same underlying SoC family. Thanks, Odelu