From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4EC81D8A0A; Thu, 8 May 2025 06:18:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746685117; cv=none; b=ZUDc6FPTjz+Wc8R595NSGk/PhHaoV/rKc9L2QDiT6lsJ3rMP9SBrK7AAYDehxCNdvkV0mGlDUZCm3mHjpbPusp69ecZCaFgapk+0fvCw4kTgPCww/BGpSpLHdcBNnClQB9mRLxBDEJZlezFrPc51U7hJWgXPLa+S2SvDi60OTB0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746685117; c=relaxed/simple; bh=4qi/P67+uIyVReLfU5vjCz6ajupbpcjoxwPILqTAti4=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=IkVQf7upDtMvxQ7lNByWAcs9LZ2TTmOt8lg9DsDjxcOYOO3LLfgoqPry5UzmD7c/u28nnOUfRXszXtW54hPixjHF9e7L7JfYibKNxKNuQuIk45yyq+eWlDBeSp1RsbzeGYMU/9oj1iQ7J1j7EEiso/4ye3s0z1Yy3/GSGsOWpKw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=UiFEZStG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UiFEZStG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1A936C4CEEE; Thu, 8 May 2025 06:18:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746685116; bh=4qi/P67+uIyVReLfU5vjCz6ajupbpcjoxwPILqTAti4=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=UiFEZStGiIcWzwH57Q4Z5xVbDrbOdjIpEJB0bMIQyEOzawyELYmi7tHEErn0dPQv2 dlxony58CRNFXVyO5ZIFM4SQZjbPjynGDXkkbEXNE3XtBUKHuXHWWL/Tt05g480fUf g5DBy8B89p+nZbYj/mYy5tgePS2f5xhK9mwgrjDwtVu0gZpMNdwJJ5BQKMr4Kn/lyN JDABKLlcdp/UFIAwuB0oSy988GOu0AH7tc5LKP/kwT8dTHQS2G0lGorZfvAU3Ipg6p edQZrzz5WVop/J/j+yeQwHU00KKuMpLZO0LktdaEMV+4iZn7uEcA5QId3hxEUmusDM UyVtnT8ZBmw0A== Message-ID: Date: Thu, 8 May 2025 08:18:30 +0200 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] dt-bindings: display/msm: add stream 1 pixel clock binding To: Abhinav Kumar , Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Mahadevan Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20241202-dp_mst_bindings-v1-0-9a9a43b0624a@quicinc.com> <20241202-dp_mst_bindings-v1-3-9a9a43b0624a@quicinc.com> <39f8e20a-e8c3-4625-abb1-9f35f416705d@kernel.org> <50820e7b-b302-4f7f-baf9-778f3db6cfff@quicinc.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 23/04/2025 04:46, Abhinav Kumar wrote: > Hi Krzysztof > > On 12/3/2024 12:04 AM, Krzysztof Kozlowski wrote: >> On 03/12/2024 04:31, Abhinav Kumar wrote: >>> On some chipsets the display port controller can support more >> >> Which chipsets? >> > > From the current list of chipsets which support DP, the following can > support more than one stream. > > qcom,sa8775p-dp > qcom,sc7280-dp > qcom,sc8180x-dp > qcom,sc8280xp-dp > qcom,sm8350-dp > qcom,sm8650-dp > qcom,sm8550-dp > qcom,sm8450-dp > qcom,sm8250-dp > qcom,sm8150-dp > > So do you also want all of these to be added in the same if block as > qcom,sa8775p-dp? That was talk in 2024. Entire context is gone if you reply after three months. I do not have even that emails in my inbox anymore. Probably I expected commit msg to mention at least some, so everyone knows which chipsets are affected here and one can verify the statements from commit msg. > >>> than one pixel stream (multi-stream transport). To support MST >>> on such chipsets, add the binding for stream 1 pixel clock for >>> display port controller. Since this mode is not supported on all >>> chipsets, add exception rules and min/max items to clearly mark >>> which chipsets support only SST mode (single stream) and which ones >>> support MST. >>> >>> Signed-off-by: Abhinav Kumar >>> --- >>> .../bindings/display/msm/dp-controller.yaml | 32 ++++++++++++++++++++++ >>> .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 9 ++++-- >>> 2 files changed, 38 insertions(+), 3 deletions(-) >>> >>> diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml >>> index 9fe2bf0484d8..650d19e58277 100644 >>> --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml >>> +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml >>> @@ -50,30 +50,38 @@ properties: >>> maxItems: 1 >>> >>> clocks: >>> + minItems: 5 >>> items: >>> - description: AHB clock to enable register access >>> - description: Display Port AUX clock >>> - description: Display Port Link clock >>> - description: Link interface clock between DP and PHY >>> - description: Display Port stream 0 Pixel clock >>> + - description: Display Port stream 1 Pixel clock >>> >>> clock-names: >>> + minItems: 5 >>> items: >>> - const: core_iface >>> - const: core_aux >>> - const: ctrl_link >>> - const: ctrl_link_iface >>> - const: stream_pixel >>> + - const: stream_1_pixel >>> >>> assigned-clocks: >>> + minItems: 2 >>> items: >>> - description: link clock source >>> - description: stream 0 pixel clock source >>> + - description: stream 1 pixel clock source >>> >>> assigned-clock-parents: >>> + minItems: 2 >>> items: >>> - description: Link clock PLL output provided by PHY block >>> - description: Stream 0 pixel clock PLL output provided by PHY block >>> + - description: Stream 1 pixel clock PLL output provided by PHY block >>> >>> phys: >>> maxItems: 1 >>> @@ -175,6 +183,30 @@ allOf: >>> required: >>> - "#sound-dai-cells" >>> >> >> Missing if: narrowing this to 5 items for other devices. >> > > OR would an else be better? Usually not, although depends how this binding is written. > > + else: > + properties: > + clocks: > + maxItems: 5 > + clock-names: > + items: > + - const: core_iface > + - const: core_aux > + - const: ctrl_link > + - const: ctrl_link_iface > + - const: stream_pixel > >>> + - if: >>> + properties: >>> + compatible: >>> + contains: >>> + enum: >>> + - qcom,sa8775p-dp >>> + >>> + then: >>> + properties: >>> + clocks: >> >> Missing minItems, otherwise it is pointless. >> > > I thought that since I have already specified the minItems as 5 > in the clocks in the section above, I need to specify only the maxItems > here? No, you need explicit constraints here. Best regards, Krzysztof