[PATCH v2 0/6] arm64: dts: qcom: qcs615: enable remoteprocs - ADSP and CDSP

[PATCH v2 0/6] arm64: dts: qcom: qcs615: enable remoteprocs - ADSP and CDSP

[Lijuan Gao]

Enable the remote processor PAS loader for QCS615 ADSP and CDSP
processors. This allows different platforms/architectures to control
(power on, load firmware, power off) those remote processors while
abstracting the hardware differences. Additionally, and add a PIL region
in IMEM so that post mortem debug tools can collect ramdumps.

Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
Changes in v2:
- Remove the qcom prefix from smp2p node name.
- Remove the unnecessary property qcom,ipc from smp2p node.
- Remove the unused node apcs: syscon.
- Remove the unused nodes from smp2p node, such as
  sleepstate_smp2p_out/in, smp2p_rdbg2_out/in, smp2p_rdbg5_out/in.
- Update the commit message for IMEM PIL info region.
- Update the remoteproc node names.
- Correct the size of register for remoteproc nodes.
- Add empty line before status properties.
- Link to v1: https://lore.kernel.org/r/20250423-add_qcs615_remoteproc_support-v1-0-a94fe8799f14@quicinc.com

---
Kyle Deng (1):
      arm64: dts: qcom: qcs615: Add mproc node for SEMP2P

Lijuan Gao (5):
      dt-bindings: remoteproc: qcom,sm8150-pas: Document QCS615 remoteproc
      dt-bindings: soc: qcom: add qcom,qcs615-imem compatible
      arm64: dts: qcom: qcs615: Add IMEM and PIL info region
      arm64: dts: qcom: qcs615: add ADSP and CDSP nodes
      arm64: dts: qcom: qcs615-ride: enable remoteprocs

 .../bindings/remoteproc/qcom,sm8150-pas.yaml       |  59 +++++----
 .../devicetree/bindings/sram/qcom,imem.yaml        |   1 +
 arch/arm64/boot/dts/qcom/qcs615-ride.dts           |  12 ++
 arch/arm64/boot/dts/qcom/qcs615.dtsi               | 143 +++++++++++++++++++++
 4 files changed, 191 insertions(+), 24 deletions(-)
---
base-commit: 08710e696081d58163c8078e0e096be6d35c5fad
change-id: 20250507-add_qcs615_remoteproc_support-c82d30f9433d

Best regards,
-- 
Lijuan Gao <quic_lijuang@quicinc.com>

[PATCH v2 1/6] dt-bindings: remoteproc: qcom,sm8150-pas: Document QCS615 remoteproc

[Lijuan Gao]

Document the components used to boot the ADSP and CDSP on the Qualcomm
QCS615 SoC. Use fallback to indicate the compatibility of the remoteproc
on the QCS615 with that on the SM8150.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
 .../bindings/remoteproc/qcom,sm8150-pas.yaml       | 59 +++++++++++++---------
 1 file changed, 35 insertions(+), 24 deletions(-)

diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml
index 56ff6386534d..caee47b52d5a 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml
@@ -15,14 +15,23 @@ description:
 
 properties:
   compatible:
-    enum:
-      - qcom,sm8150-adsp-pas
-      - qcom,sm8150-cdsp-pas
-      - qcom,sm8150-mpss-pas
-      - qcom,sm8150-slpi-pas
-      - qcom,sm8250-adsp-pas
-      - qcom,sm8250-cdsp-pas
-      - qcom,sm8250-slpi-pas
+    oneOf:
+      - items:
+          - enum:
+              - qcom,qcs615-adsp-pas
+          - const: qcom,sm8150-adsp-pas
+      - items:
+          - enum:
+              - qcom,qcs615-cdsp-pas
+          - const: qcom,sm8150-cdsp-pas
+      - enum:
+          - qcom,sm8150-adsp-pas
+          - qcom,sm8150-cdsp-pas
+          - qcom,sm8150-mpss-pas
+          - qcom,sm8150-slpi-pas
+          - qcom,sm8250-adsp-pas
+          - qcom,sm8250-cdsp-pas
+          - qcom,sm8250-slpi-pas
 
   reg:
     maxItems: 1
@@ -59,16 +68,17 @@ allOf:
   - if:
       properties:
         compatible:
-          enum:
-            - qcom,sc8180x-adsp-pas
-            - qcom,sc8180x-cdsp-pas
-            - qcom,sc8180x-slpi-pas
-            - qcom,sm8150-adsp-pas
-            - qcom,sm8150-cdsp-pas
-            - qcom,sm8150-slpi-pas
-            - qcom,sm8250-adsp-pas
-            - qcom,sm8250-cdsp-pas
-            - qcom,sm8250-slpi-pas
+          contains:
+            enum:
+              - qcom,sc8180x-adsp-pas
+              - qcom,sc8180x-cdsp-pas
+              - qcom,sc8180x-slpi-pas
+              - qcom,sm8150-adsp-pas
+              - qcom,sm8150-cdsp-pas
+              - qcom,sm8150-slpi-pas
+              - qcom,sm8250-adsp-pas
+              - qcom,sm8250-cdsp-pas
+              - qcom,sm8250-slpi-pas
     then:
       properties:
         interrupts:
@@ -85,12 +95,13 @@ allOf:
   - if:
       properties:
         compatible:
-          enum:
-            - qcom,sc8180x-adsp-pas
-            - qcom,sc8180x-cdsp-pas
-            - qcom,sm8150-adsp-pas
-            - qcom,sm8150-cdsp-pas
-            - qcom,sm8250-cdsp-pas
+          contains:
+            enum:
+              - qcom,sc8180x-adsp-pas
+              - qcom,sc8180x-cdsp-pas
+              - qcom,sm8150-adsp-pas
+              - qcom,sm8150-cdsp-pas
+              - qcom,sm8250-cdsp-pas
     then:
       properties:
         power-domains:

-- 
2.46.0

[PATCH v2 2/6] dt-bindings: soc: qcom: add qcom,qcs615-imem compatible

[Lijuan Gao]

Document qcom,qcs615-imem compatible. It has a child node for debugging
purposes.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
 Documentation/devicetree/bindings/sram/qcom,imem.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml b/Documentation/devicetree/bindings/sram/qcom,imem.yaml
index 2711f90d9664..dc3b5a69b925 100644
--- a/Documentation/devicetree/bindings/sram/qcom,imem.yaml
+++ b/Documentation/devicetree/bindings/sram/qcom,imem.yaml
@@ -22,6 +22,7 @@ properties:
           - qcom,msm8974-imem
           - qcom,msm8976-imem
           - qcom,qcs404-imem
+          - qcom,qcs615-imem
           - qcom,qcs8300-imem
           - qcom,qdu1000-imem
           - qcom,sa8775p-imem

-- 
2.46.0

[PATCH v2 3/6] arm64: dts: qcom: qcs615: Add mproc node for SEMP2P

[Lijuan Gao]

From: Kyle Deng <quic_chunkaid@quicinc.com>

The Shared Memory Point to Point (SMP2P) protocol facilitates
communication of a single 32-bit value between two processors.
Add these two nodes for remoteproc enablement on QCS615 SoC.

Signed-off-by: Kyle Deng <quic_chunkaid@quicinc.com>
Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs615.dtsi | 43 ++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index 7c377f3402c1..53661e3a852e 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -332,6 +332,49 @@ mc_virt: interconnect-2 {
 		qcom,bcm-voters = <&apps_bcm_voter>;
 	};
 
+	smp2p-adsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <443>, <429>;
+		interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&apss_shared 26>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <2>;
+
+		adsp_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		adsp_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smp2p-cdsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <94>, <432>;
+		interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&apss_shared 6>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <5>;
+
+		cdsp_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		cdsp_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+	};
+
 	qup_opp_table: opp-table-qup {
 		compatible = "operating-points-v2";
 		opp-shared;

-- 
2.46.0

[PATCH v2 4/6] arm64: dts: qcom: qcs615: Add IMEM and PIL info region

[Lijuan Gao]

Add a simple-mfd representing IMEM on QCS615 and define the PIL
relocation info region as its child. The PIL region in IMEM is used to
communicate load addresses of remoteproc to post mortem debug tools, so
that these tools can collect ramdumps.

Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs615.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index 53661e3a852e..fefdb0fd66f7 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -3266,6 +3266,20 @@ sram@c3f0000 {
 			reg = <0x0 0x0c3f0000 0x0 0x400>;
 		};
 
+		sram@146aa000 {
+			compatible = "qcom,qcs615-imem", "syscon", "simple-mfd";
+			reg = <0x0 0x146aa000 0x0 0x1000>;
+			ranges = <0 0 0x146aa000 0x1000>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			pil-reloc@94c {
+				compatible = "qcom,pil-reloc-info";
+				reg = <0x94c 0xc8>;
+			};
+		};
+
 		apps_smmu: iommu@15000000 {
 			compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500";
 			reg = <0x0 0x15000000 0x0 0x80000>;

-- 
2.46.0

[PATCH v2 5/6] arm64: dts: qcom: qcs615: add ADSP and CDSP nodes

[Lijuan Gao]

Add nodes for remoteprocs: ADSP and CDSP for QCS615 SoC to enable proper
remoteproc functionality.

Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs615.dtsi | 86 ++++++++++++++++++++++++++++++++++++
 1 file changed, 86 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index fefdb0fd66f7..5e4565137396 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -472,6 +472,16 @@ smem_region: smem@86000000 {
 			no-map;
 			hwlocks = <&tcsr_mutex 3>;
 		};
+
+		rproc_cdsp_mem: rproc-cdsp@93b00000 {
+			reg = <0x0 0x93b00000 0x0 0x1e00000>;
+			no-map;
+		};
+
+		rproc_adsp_mem: rproc-adsp@95900000 {
+			reg = <0x0 0x95900000 0x0 0x1e00000>;
+			no-map;
+		};
 	};
 
 	soc: soc@0 {
@@ -3093,6 +3103,44 @@ cti@7900000 {
 			clock-names = "apb_pclk";
 		};
 
+		remoteproc_cdsp: remoteproc@8300000 {
+			compatible = "qcom,qcs615-cdsp-pas", "qcom,sm8150-cdsp-pas";
+			reg = <0x0 0x08300000 0x0 0x4040>;
+
+			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
+					      <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog",
+					  "fatal",
+					  "ready",
+					  "handover",
+					  "stop-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			power-domains = <&rpmhpd RPMHPD_CX>;
+			power-domain-names = "cx";
+
+			memory-region = <&rproc_cdsp_mem>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&cdsp_smp2p_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			glink-edge {
+				interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
+				mboxes = <&apss_shared 4>;
+				label = "cdsp";
+				qcom,remote-pid = <5>;
+			};
+		};
+
 		pmu@90b6300 {
 			compatible = "qcom,qcs615-cpu-bwmon", "qcom,sdm845-bwmon";
 			reg = <0x0 0x090b6300 0x0 0x600>;
@@ -3727,6 +3775,44 @@ usb_2_dwc3: usb@a800000 {
 				maximum-speed = "high-speed";
 			};
 		};
+
+		remoteproc_adsp: remoteproc@62400000 {
+			compatible = "qcom,qcs615-adsp-pas", "qcom,sm8150-adsp-pas";
+			reg = <0x0 0x62400000 0x0 0x4040>;
+
+			interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
+					      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog",
+					  "fatal",
+					  "ready",
+					  "handover",
+					  "stop-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			power-domains = <&rpmhpd RPMHPD_CX>;
+			power-domain-names = "cx";
+
+			memory-region = <&rproc_adsp_mem>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&adsp_smp2p_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			glink_edge: glink-edge {
+				interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
+				mboxes = <&apss_shared 24>;
+				label = "lpass";
+				qcom,remote-pid = <2>;
+			};
+		};
 	};
 
 	arch_timer: timer {

-- 
2.46.0

[PATCH v2 6/6] arm64: dts: qcom: qcs615-ride: enable remoteprocs

[Lijuan Gao]

Enable all remoteproc nodes on the qcs615-ride board and point to the
appropriate firmware files to allow proper functioning of the remote
processors.

Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs615-ride.dts | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
index 2b5aa3c66867..a6652e4817d1 100644
--- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
@@ -240,6 +240,18 @@ &qupv3_id_0 {
 	status = "okay";
 };
 
+&remoteproc_adsp {
+	firmware-name = "qcom/qcs615/adsp.mbn";
+
+	status = "okay";
+};
+
+&remoteproc_cdsp {
+	firmware-name = "qcom/qcs615/cdsp.mbn";
+
+	status = "okay";
+};
+
 &rpmhcc {
 	clocks = <&xo_board_clk>;
 };

-- 
2.46.0

Re: [PATCH v2 3/6] arm64: dts: qcom: qcs615: Add mproc node for SEMP2P

[Konrad Dybcio]

On 5/7/25 12:26 PM, Lijuan Gao wrote:
> From: Kyle Deng <quic_chunkaid@quicinc.com>
> 
> The Shared Memory Point to Point (SMP2P) protocol facilitates
> communication of a single 32-bit value between two processors.
> Add these two nodes for remoteproc enablement on QCS615 SoC.
> 
> Signed-off-by: Kyle Deng <quic_chunkaid@quicinc.com>
> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs615.dtsi | 43 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 43 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> index 7c377f3402c1..53661e3a852e 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -332,6 +332,49 @@ mc_virt: interconnect-2 {
>  		qcom,bcm-voters = <&apps_bcm_voter>;
>  	};
>  
> +	smp2p-adsp {
> +		compatible = "qcom,smp2p";
> +		qcom,smem = <443>, <429>;
> +		interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
> +		mboxes = <&apss_shared 26>;

26 will poke at the SLPI instead

Konrad

Re: [PATCH v2 4/6] arm64: dts: qcom: qcs615: Add IMEM and PIL info region

[Konrad Dybcio]

On 5/7/25 12:26 PM, Lijuan Gao wrote:
> Add a simple-mfd representing IMEM on QCS615 and define the PIL
> relocation info region as its child. The PIL region in IMEM is used to
> communicate load addresses of remoteproc to post mortem debug tools, so
> that these tools can collect ramdumps.
> 
> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs615.dtsi | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> index 53661e3a852e..fefdb0fd66f7 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -3266,6 +3266,20 @@ sram@c3f0000 {
>  			reg = <0x0 0x0c3f0000 0x0 0x400>;
>  		};
>  
> +		sram@146aa000 {
> +			compatible = "qcom,qcs615-imem", "syscon", "simple-mfd";
> +			reg = <0x0 0x146aa000 0x0 0x1000>;

0x14680000 0x2c000

Re: [PATCH v2 5/6] arm64: dts: qcom: qcs615: add ADSP and CDSP nodes

[Konrad Dybcio]

On 5/7/25 12:26 PM, Lijuan Gao wrote:
> Add nodes for remoteprocs: ADSP and CDSP for QCS615 SoC to enable proper
> remoteproc functionality.
> 
> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v2 6/6] arm64: dts: qcom: qcs615-ride: enable remoteprocs

[Konrad Dybcio]

On 5/7/25 12:26 PM, Lijuan Gao wrote:
> Enable all remoteproc nodes on the qcs615-ride board and point to the
> appropriate firmware files to allow proper functioning of the remote
> processors.
> 
> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
> ---


Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v2 4/6] arm64: dts: qcom: qcs615: Add IMEM and PIL info region

[Lijuan Gao]

在 5/8/2025 10:41 PM, Konrad Dybcio 写道:
> On 5/7/25 12:26 PM, Lijuan Gao wrote:
>> Add a simple-mfd representing IMEM on QCS615 and define the PIL
>> relocation info region as its child. The PIL region in IMEM is used to
>> communicate load addresses of remoteproc to post mortem debug tools, so
>> that these tools can collect ramdumps.
>>
>> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/qcs615.dtsi | 14 ++++++++++++++
>>   1 file changed, 14 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> index 53661e3a852e..fefdb0fd66f7 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> @@ -3266,6 +3266,20 @@ sram@c3f0000 {
>>   			reg = <0x0 0x0c3f0000 0x0 0x400>;
>>   		};
>>   
>> +		sram@146aa000 {
>> +			compatible = "qcom,qcs615-imem", "syscon", "simple-mfd";
>> +			reg = <0x0 0x146aa000 0x0 0x1000>;
> 
> 0x14680000 0x2c000

I checked the latest datasheet, the Shared IMEM address is 0x146aa000 
and its size is 0x1000, 0x14680000 is the start address of IMEM layout. 
The shared IMEM is used for debugging purposes, while the others parts 
are dedicated.

-- 
Thx and BRs
Lijuan Gao

Re: [PATCH v2 3/6] arm64: dts: qcom: qcs615: Add mproc node for SEMP2P

[Lijuan Gao]

在 5/8/2025 10:40 PM, Konrad Dybcio 写道:
> On 5/7/25 12:26 PM, Lijuan Gao wrote:
>> From: Kyle Deng <quic_chunkaid@quicinc.com>
>>
>> The Shared Memory Point to Point (SMP2P) protocol facilitates
>> communication of a single 32-bit value between two processors.
>> Add these two nodes for remoteproc enablement on QCS615 SoC.
>>
>> Signed-off-by: Kyle Deng <quic_chunkaid@quicinc.com>
>> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/qcs615.dtsi | 43 ++++++++++++++++++++++++++++++++++++
>>   1 file changed, 43 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> index 7c377f3402c1..53661e3a852e 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> @@ -332,6 +332,49 @@ mc_virt: interconnect-2 {
>>   		qcom,bcm-voters = <&apps_bcm_voter>;
>>   	};
>>   
>> +	smp2p-adsp {
>> +		compatible = "qcom,smp2p";
>> +		qcom,smem = <443>, <429>;
>> +		interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
>> +		mboxes = <&apss_shared 26>;
> 
> 26 will poke at the SLPI instead

SLPI has not been enabled in QCS615, so the sensor will be in ADSP.  And 
26 is being used dowstream, so it should be correct.
> 
> Konrad

-- 
Thx and BRs
Lijuan Gao

Re: [PATCH v2 3/6] arm64: dts: qcom: qcs615: Add mproc node for SEMP2P

[Konrad Dybcio]

On 5/9/25 10:22 AM, Lijuan Gao wrote:
> 
> 
> 在 5/8/2025 10:40 PM, Konrad Dybcio 写道:
>> On 5/7/25 12:26 PM, Lijuan Gao wrote:
>>> From: Kyle Deng <quic_chunkaid@quicinc.com>
>>>
>>> The Shared Memory Point to Point (SMP2P) protocol facilitates
>>> communication of a single 32-bit value between two processors.
>>> Add these two nodes for remoteproc enablement on QCS615 SoC.
>>>
>>> Signed-off-by: Kyle Deng <quic_chunkaid@quicinc.com>
>>> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
>>> ---
>>>   arch/arm64/boot/dts/qcom/qcs615.dtsi | 43 ++++++++++++++++++++++++++++++++++++
>>>   1 file changed, 43 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>> index 7c377f3402c1..53661e3a852e 100644
>>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>> @@ -332,6 +332,49 @@ mc_virt: interconnect-2 {
>>>           qcom,bcm-voters = <&apps_bcm_voter>;
>>>       };
>>>   +    smp2p-adsp {
>>> +        compatible = "qcom,smp2p";
>>> +        qcom,smem = <443>, <429>;
>>> +        interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
>>> +        mboxes = <&apss_shared 26>;
>>
>> 26 will poke at the SLPI instead
> 
> SLPI has not been enabled in QCS615, so the sensor will be in ADSP.  And 26 is being used dowstream, so it should be correct.

Please check in with the relevant folks and leave a comment such as

/* On this platform, bit 26 (normally SLPI) is repurposed for ADSP */

if it's indeed correct

Konrad

Re: [PATCH v2 4/6] arm64: dts: qcom: qcs615: Add IMEM and PIL info region

[Konrad Dybcio]

On 5/9/25 9:37 AM, Lijuan Gao wrote:
> 
> 
> 在 5/8/2025 10:41 PM, Konrad Dybcio 写道:
>> On 5/7/25 12:26 PM, Lijuan Gao wrote:
>>> Add a simple-mfd representing IMEM on QCS615 and define the PIL
>>> relocation info region as its child. The PIL region in IMEM is used to
>>> communicate load addresses of remoteproc to post mortem debug tools, so
>>> that these tools can collect ramdumps.
>>>
>>> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
>>> ---
>>>   arch/arm64/boot/dts/qcom/qcs615.dtsi | 14 ++++++++++++++
>>>   1 file changed, 14 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>> index 53661e3a852e..fefdb0fd66f7 100644
>>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>> @@ -3266,6 +3266,20 @@ sram@c3f0000 {
>>>               reg = <0x0 0x0c3f0000 0x0 0x400>;
>>>           };
>>>   +        sram@146aa000 {
>>> +            compatible = "qcom,qcs615-imem", "syscon", "simple-mfd";
>>> +            reg = <0x0 0x146aa000 0x0 0x1000>;
>>
>> 0x14680000 0x2c000
> 
> I checked the latest datasheet, the Shared IMEM address is 0x146aa000 and its size is 0x1000, 0x14680000 is the start address of IMEM layout. The shared IMEM is used for debugging purposes, while the others parts are dedicated.

Even if we don't use the entirety of it, it's good to describe
the whole block

Konrad

Re: [PATCH v2 3/6] arm64: dts: qcom: qcs615: Add mproc node for SEMP2P

[Lijuan Gao]

在 5/9/2025 4:53 PM, Konrad Dybcio 写道:
> On 5/9/25 10:22 AM, Lijuan Gao wrote:
>>
>>
>> 在 5/8/2025 10:40 PM, Konrad Dybcio 写道:
>>> On 5/7/25 12:26 PM, Lijuan Gao wrote:
>>>> From: Kyle Deng <quic_chunkaid@quicinc.com>
>>>>
>>>> The Shared Memory Point to Point (SMP2P) protocol facilitates
>>>> communication of a single 32-bit value between two processors.
>>>> Add these two nodes for remoteproc enablement on QCS615 SoC.
>>>>
>>>> Signed-off-by: Kyle Deng <quic_chunkaid@quicinc.com>
>>>> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
>>>> ---
>>>>    arch/arm64/boot/dts/qcom/qcs615.dtsi | 43 ++++++++++++++++++++++++++++++++++++
>>>>    1 file changed, 43 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>>> index 7c377f3402c1..53661e3a852e 100644
>>>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>>> @@ -332,6 +332,49 @@ mc_virt: interconnect-2 {
>>>>            qcom,bcm-voters = <&apps_bcm_voter>;
>>>>        };
>>>>    +    smp2p-adsp {
>>>> +        compatible = "qcom,smp2p";
>>>> +        qcom,smem = <443>, <429>;
>>>> +        interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
>>>> +        mboxes = <&apss_shared 26>;
>>>
>>> 26 will poke at the SLPI instead
>>
>> SLPI has not been enabled in QCS615, so the sensor will be in ADSP.  And 26 is being used dowstream, so it should be correct.
> 
> Please check in with the relevant folks and leave a comment such as
> 
> /* On this platform, bit 26 (normally SLPI) is repurposed for ADSP */
> 
> if it's indeed correct
> 
> Konrad

Yes, I have already confirmed the above information with the relevant 
folks. I will add this comment in the next patch.

-- 
Thx and BRs
Lijuan Gao

Re: [PATCH v2 4/6] arm64: dts: qcom: qcs615: Add IMEM and PIL info region

[Lijuan Gao]

在 5/9/2025 4:54 PM, Konrad Dybcio 写道:
> On 5/9/25 9:37 AM, Lijuan Gao wrote:
>>
>>
>> 在 5/8/2025 10:41 PM, Konrad Dybcio 写道:
>>> On 5/7/25 12:26 PM, Lijuan Gao wrote:
>>>> Add a simple-mfd representing IMEM on QCS615 and define the PIL
>>>> relocation info region as its child. The PIL region in IMEM is used to
>>>> communicate load addresses of remoteproc to post mortem debug tools, so
>>>> that these tools can collect ramdumps.
>>>>
>>>> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
>>>> ---
>>>>    arch/arm64/boot/dts/qcom/qcs615.dtsi | 14 ++++++++++++++
>>>>    1 file changed, 14 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>>> index 53661e3a852e..fefdb0fd66f7 100644
>>>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>>> @@ -3266,6 +3266,20 @@ sram@c3f0000 {
>>>>                reg = <0x0 0x0c3f0000 0x0 0x400>;
>>>>            };
>>>>    +        sram@146aa000 {
>>>> +            compatible = "qcom,qcs615-imem", "syscon", "simple-mfd";
>>>> +            reg = <0x0 0x146aa000 0x0 0x1000>;
>>>
>>> 0x14680000 0x2c000
>>
>> I checked the latest datasheet, the Shared IMEM address is 0x146aa000 and its size is 0x1000, 0x14680000 is the start address of IMEM layout. The shared IMEM is used for debugging purposes, while the others parts are dedicated.
> 
> Even if we don't use the entirety of it, it's good to describe
> the whole block
> 
> Konrad

According to the definitions on all existing upstream platforms, this 
imem points to the shared imem. Should we stay consistent?

-- 
Thx and BRs
Lijuan Gao

Re: [PATCH v2 4/6] arm64: dts: qcom: qcs615: Add IMEM and PIL info region

[Konrad Dybcio]

On 5/12/25 5:20 AM, Lijuan Gao wrote:
> 
> 
> 在 5/9/2025 4:54 PM, Konrad Dybcio 写道:
>> On 5/9/25 9:37 AM, Lijuan Gao wrote:
>>>
>>>
>>> 在 5/8/2025 10:41 PM, Konrad Dybcio 写道:
>>>> On 5/7/25 12:26 PM, Lijuan Gao wrote:
>>>>> Add a simple-mfd representing IMEM on QCS615 and define the PIL
>>>>> relocation info region as its child. The PIL region in IMEM is used to
>>>>> communicate load addresses of remoteproc to post mortem debug tools, so
>>>>> that these tools can collect ramdumps.
>>>>>
>>>>> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
>>>>> ---
>>>>>    arch/arm64/boot/dts/qcom/qcs615.dtsi | 14 ++++++++++++++
>>>>>    1 file changed, 14 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>>>> index 53661e3a852e..fefdb0fd66f7 100644
>>>>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>>>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>>>> @@ -3266,6 +3266,20 @@ sram@c3f0000 {
>>>>>                reg = <0x0 0x0c3f0000 0x0 0x400>;
>>>>>            };
>>>>>    +        sram@146aa000 {
>>>>> +            compatible = "qcom,qcs615-imem", "syscon", "simple-mfd";
>>>>> +            reg = <0x0 0x146aa000 0x0 0x1000>;
>>>>
>>>> 0x14680000 0x2c000
>>>
>>> I checked the latest datasheet, the Shared IMEM address is 0x146aa000 and its size is 0x1000, 0x14680000 is the start address of IMEM layout. The shared IMEM is used for debugging purposes, while the others parts are dedicated.
>>
>> Even if we don't use the entirety of it, it's good to describe
>> the whole block
>>
>> Konrad
> 
> According to the definitions on all existing upstream platforms, this imem points to the shared imem. Should we stay consistent?

That is because everyone kept copying over whatever the downstream
kernel did ;)

Let's describe the whole region - at best, it doesn't hurt

Konrad

Re: [PATCH v2 4/6] arm64: dts: qcom: qcs615: Add IMEM and PIL info region

[Lijuan Gao]

在 5/13/2025 3:10 AM, Konrad Dybcio 写道:
> On 5/12/25 5:20 AM, Lijuan Gao wrote:
>>
>>
>> 在 5/9/2025 4:54 PM, Konrad Dybcio 写道:
>>> On 5/9/25 9:37 AM, Lijuan Gao wrote:
>>>>
>>>>
>>>> 在 5/8/2025 10:41 PM, Konrad Dybcio 写道:
>>>>> On 5/7/25 12:26 PM, Lijuan Gao wrote:
>>>>>> Add a simple-mfd representing IMEM on QCS615 and define the PIL
>>>>>> relocation info region as its child. The PIL region in IMEM is used to
>>>>>> communicate load addresses of remoteproc to post mortem debug tools, so
>>>>>> that these tools can collect ramdumps.
>>>>>>
>>>>>> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
>>>>>> ---
>>>>>>     arch/arm64/boot/dts/qcom/qcs615.dtsi | 14 ++++++++++++++
>>>>>>     1 file changed, 14 insertions(+)
>>>>>>
>>>>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>>>>> index 53661e3a852e..fefdb0fd66f7 100644
>>>>>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>>>>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>>>>> @@ -3266,6 +3266,20 @@ sram@c3f0000 {
>>>>>>                 reg = <0x0 0x0c3f0000 0x0 0x400>;
>>>>>>             };
>>>>>>     +        sram@146aa000 {
>>>>>> +            compatible = "qcom,qcs615-imem", "syscon", "simple-mfd";
>>>>>> +            reg = <0x0 0x146aa000 0x0 0x1000>;
>>>>>
>>>>> 0x14680000 0x2c000
>>>>
>>>> I checked the latest datasheet, the Shared IMEM address is 0x146aa000 and its size is 0x1000, 0x14680000 is the start address of IMEM layout. The shared IMEM is used for debugging purposes, while the others parts are dedicated.
>>>
>>> Even if we don't use the entirety of it, it's good to describe
>>> the whole block
>>>
>>> Konrad
>>
>> According to the definitions on all existing upstream platforms, this imem points to the shared imem. Should we stay consistent?
> 
> That is because everyone kept copying over whatever the downstream
> kernel did ;)
> 
> Let's describe the whole region - at best, it doesn't hurt
> 
> Konrad

Understood, it will be updated in the next patch.

-- 
Thx and BRs
Lijuan Gao