From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Komal Bajaj <quic_kbajaj@quicinc.com>,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Abel Vesa <abel.vesa@linaro.org>,
Rishabh Bhatnagar <rishabhb@codeaurora.org>,
Prakash Ranjan <saiprakash.ranjan@codeaurora.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Andy Gross <agross@kernel.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-msm@vger.kernel.org,
Mukesh Ojha <quic_mojha@quicinc.com>
Subject: Re: [PATCH v2 2/5] dt-bindings: arm: msm: Add bindings for multi channel DDR in LLCC
Date: Thu, 6 Apr 2023 11:34:54 +0200 [thread overview]
Message-ID: <f9728472-0dda-2fb2-1753-e9c039afa4c1@linaro.org> (raw)
In-Reply-To: <c8f3499f-d927-6657-c7c6-732ed2222525@quicinc.com>
On 06/04/2023 11:19, Komal Bajaj wrote:
>
>>>>
>>>> interrupts:
>>>> maxItems: 1
>>>>
>>>> + multi-ch-bit-off:
>>>> + items:
>>>> + - description: Specifies the offset in bits into the multi_channel_register
>>>> + and the number of bits used to decide which LLCC configuration
>>>> + to use
>>> There are here few issues.
>>> First, I don't fully understand the property. What is an LLCC
>>> configuration? Like some fused values?
>
> There are different configuration for LLCC based on the number of
> DDR channel it uses. Here, we are basically trying to get information
> about the same.
>
>>>
>>> Second, don't make it a register specific, it will not scale easily to
>>> any new version of this interface. Although how this should look like
>>> depends on what is it.
>
> LLCC driver can only get DDR channel information from the register.
And why would that exactly matter to DT? How does it solve my concern
that your approach does not scale?
Best regards,
Krzysztof
next prev parent reply other threads:[~2023-04-06 9:35 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-13 12:40 [PATCH v2 0/5] soc: qcom: llcc: Add support for QDU1000/QRU1000 Komal Bajaj
2023-03-13 12:40 ` [PATCH v2 1/5] soc: qcom: llcc: Refactor llcc driver to support multiple configuration Komal Bajaj
2023-04-07 5:52 ` Abel Vesa
2023-03-13 12:40 ` [PATCH v2 2/5] dt-bindings: arm: msm: Add bindings for multi channel DDR in LLCC Komal Bajaj
2023-03-14 14:10 ` Rob Herring
2023-03-15 7:41 ` Krzysztof Kozlowski
2023-03-15 13:48 ` Manivannan Sadhasivam
[not found] ` <c8f3499f-d927-6657-c7c6-732ed2222525@quicinc.com>
2023-04-06 9:34 ` Krzysztof Kozlowski [this message]
2023-04-06 11:03 ` Mukesh Ojha
2023-04-06 9:52 ` Mukesh Ojha
2023-03-13 12:40 ` [PATCH v2 3/5] dt-bindings: arm: msm: Add LLCC compatible for QDU1000/QRU1000 Komal Bajaj
2023-03-13 12:40 ` [PATCH v2 4/5] soc: qcom: Add LLCC support for multi channel DDR Komal Bajaj
2023-03-14 23:23 ` kernel test robot
2023-03-15 7:34 ` Krzysztof Kozlowski
2023-03-15 14:08 ` Manivannan Sadhasivam
2023-03-13 12:40 ` [PATCH v2 5/5] soc: qcom: llcc: Add QDU1000 and QRU1000 LLCC support Komal Bajaj
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