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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-67ef0b3ba35sm509875a12.2.2026.05.08.03.32.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 08 May 2026 03:32:43 -0700 (PDT) Message-ID: Date: Fri, 8 May 2026 12:32:41 +0200 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] of: property: Create devlink between PCI Host bridge and Root Port supplies To: Manivannan Sadhasivam , robh@kernel.org, saravanak@kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, qiang.yu@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, Bjorn Andersson References: <20260506075625.8490-1-manivannan.sadhasivam@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260506075625.8490-1-manivannan.sadhasivam@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: qdwXRifXnTR2U7xqPiowV5M7q2KKS0L4 X-Authority-Analysis: v=2.4 cv=Nd/WEWD4 c=1 sm=1 tr=0 ts=69fdbbce cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=8Pzyt-o0a4R5NFuvPhkA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA4MDEwOSBTYWx0ZWRfXwegbjkHQqGA2 cYgZfJc1XjkZf9+SujKo8Y120Kn2nTjwE2rki/KibH9UPoEiNZVHIQ/fAXecNSgjKff5f3Pi21k 7+vKyLhBHmJjpxhSFAT6LKoTpPlScCRCwJMw5e1fm2QilsLblfrgYP5nUDsKP/RSFmzLgGTA8Wi o0JS4Tl91HtFMUW2DNXaKdeoaFuIy6SY5cmCDQIeSUntdGF4r6bHZ6vD0SF7496IiKxrEdF2o3j 1iVbKQxnQkoLcVY/TWC18OPJD94dwf9kCVLgfW6/KC3Mpe7UxNyyND7aQBYfmBctPN6Uy7spJEw gTjvOMubt3wQnRWcwMCKY5pqiKgcRwSRkT7wBiB/LJtM5Mi+Mr+SWDaKgw3HWk/4115BuOBRnWu FGJa6p8EowvWkAsV72bryWzSXr3VeA0nZqkkdH1E41X6JY9VnNbhjE3ViJt4ocd87YdoS64hegX 5BlidDRXXHHn5qxio9w== X-Proofpoint-GUID: qdwXRifXnTR2U7xqPiowV5M7q2KKS0L4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-07_02,2026-05-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 phishscore=0 clxscore=1015 spamscore=0 priorityscore=1501 adultscore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605080109 On 5/6/26 9:56 AM, Manivannan Sadhasivam wrote: > Recently, devicetree started to represent the PCI Host bridge supplies like > PHY in the Root Port nodes as seen in commit 38fcbfbd4207 > ("dt-bindings: PCI: qcom: Move PHY & reset GPIO to Root Port node"). But > the Host bridge drivers still control the Root Port supplies as a part of > their controller initialization/deinitialization sequence. > > So the Host bridge drivers end up parsing the Root Port supplies in their > probe() and control them. A downside to this approach is that the devlink > dependency between the suppliers and Host bridge is completely broken. Due > to this, the driver core probes the Host bridge drivers even if the > supplies are not ready, causing probe deferrals and setup teardowns in > Host bridge probe(). > > These probe deferrals sometime happen over 1000 times (as reported in Qcom > Glymur platform) leading to a waste of CPU resources and increase in boot > time. So to fix these unnecessary deferrals, create devlink between the > Host bridge and Root Port supplies in of_fwnode_add_links(). This will > allow the driver core to probe the Host bridge drivers only when all Root > Port supplies are available. > > Reported-by: Bjorn Andersson > Signed-off-by: Manivannan Sadhasivam > --- [...] > + /* > + * Since the host bridge drivers parse and control the Root Port > + * supplies, create a devlink between host bridge and Root Port > + * supplies. This will prevent the host bridge drivers from being > + * probed before the supplies become available. > + * > + * For checking the host bridge node, first ensure that it is a PCI node > + * and its parent is not a PCI node. Only host bridge nodes will have > + * this structure. > + */ > + if (of_node_is_type(con_np, "pci") && !of_node_is_type(con_np->parent, "pci")) { > + for_each_available_child_of_node_scoped(con_np, child) { > + if (of_node_is_type(child, "pci")) { Doesn't this go a level too deep now? (a change vs v1) for example, in x1e80100.dtsi: con_np = &pcie3_port0 con_np->parent = &pcie3 And I think the code now looks for device(such that device_type="pci") *under* &pcie3_port0 Konrad > + for_each_property_of_node(child, p) > + of_link_property(child, con_np, p->name); > + } > + } > + } > > return 0; > }