From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BEB9C41513 for ; Wed, 9 Aug 2023 06:35:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229658AbjHIGfx (ORCPT ); Wed, 9 Aug 2023 02:35:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229445AbjHIGfx (ORCPT ); Wed, 9 Aug 2023 02:35:53 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A428C10CF; Tue, 8 Aug 2023 23:35:52 -0700 (PDT) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3795rIvr025364; Wed, 9 Aug 2023 06:35:33 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=qcppdkim1; bh=hfjlnlx0runIdLBlGSK1aRkvMDJinh0LBL7Uvk7JltU=; b=ckahSk94TW7/X6Gyx9wDDThgenHCMXLHNalbxOYz2HuYp4A5KwFLCgOXkHy2b6ASyW0f 1pcsuQRexrgzoWYp8KB0cYRx99D4dKbTZKn1ms4Qmc0fBnt8tjy1IclhmmM1VUTmhnhf 9VkMOLy6hJSMwkels9XKH8zak8HgdVwhxBq322WtbTYmZio6FIieY8qcHO4vjhc7ubby Rb/0cZW61pMlC09ls7hJF9CsjZPwCdtEAiZWq2I2qQBUzfHbd4kIl2LCl3SZK+C1fnUa VoSqOGs/N1hIYu3XkkWKhCjTrWsVHaXELBpiOsf9huF7uzFzZex/PrBn9CC1LEV9Ihab rQ== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3sc0050jsg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 09 Aug 2023 06:35:33 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3796ZWoa032504 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 9 Aug 2023 06:35:32 GMT Received: from [10.239.133.211] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Tue, 8 Aug 2023 23:35:27 -0700 Message-ID: Date: Wed, 9 Aug 2023 14:35:25 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.14.0 Subject: Re: [PATCH v7 06/13] coresight-tpdm: Add reset node to TPDM node Content-Language: en-US To: Suzuki K Poulose , Mathieu Poirier , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski CC: Jinlong Mao , Leo Yan , "Greg Kroah-Hartman" , , , , , Tingwei Zhang , Yuanfang Zhang , Trilok Soni , Hao Zhang , , References: <1690269353-10829-1-git-send-email-quic_taozha@quicinc.com> <1690269353-10829-7-git-send-email-quic_taozha@quicinc.com> From: Tao Zhang In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: gvuupjJ0wwhCJtPR1ppDwnlwGEfxRrw2 X-Proofpoint-GUID: gvuupjJ0wwhCJtPR1ppDwnlwGEfxRrw2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-09_04,2023-08-08_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 bulkscore=0 mlxscore=0 adultscore=0 phishscore=0 clxscore=1015 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308090058 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 8/7/2023 5:36 PM, Suzuki K Poulose wrote: > On 25/07/2023 08:15, Tao Zhang wrote: >> TPDM device need a node to reset the configurations and status of >> it. This change provides a node to reset the configurations and >> disable the TPDM if it has been enabled. >> >> Signed-off-by: Tao Zhang >> --- >>   .../ABI/testing/sysfs-bus-coresight-devices-tpdm   | 10 ++++++++++ >>   drivers/hwtracing/coresight/coresight-tpdm.c       | 22 >> ++++++++++++++++++++++ >>   2 files changed, 32 insertions(+) >> >> diff --git >> a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >> b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >> index 4a58e64..dbc2fbd0 100644 >> --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >> @@ -11,3 +11,13 @@ Description: >>           Accepts only one of the 2 values -  1 or 2. >>           1 : Generate 64 bits data >>           2 : Generate 32 bits data >> + >> +What:        /sys/bus/coresight/devices//reset >> +Date:        March 2023 >> +KernelVersion    6.5 > > >> +Contact:    Jinlong Mao (QUIC) , Tao Zhang >> (QUIC) >> +Description: >> +        (Write) Reset the dataset of the tpdm, and disable the tpdm. > > Please fix this, we don't disable TPDM. If it only ever resets the > datasets, please could we rename this as such ? > >  i.e., reset_dataset or reset_dsb_data ? Sure, I will update this in the next patch series. > >> + >> +        Accepts only one value -  1. >> +        1 : Reset the dataset of the tpdm >> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c >> b/drivers/hwtracing/coresight/coresight-tpdm.c >> index 52aa48a6..acc3eea 100644 >> --- a/drivers/hwtracing/coresight/coresight-tpdm.c >> +++ b/drivers/hwtracing/coresight/coresight-tpdm.c >> @@ -159,6 +159,27 @@ static int tpdm_datasets_setup(struct >> tpdm_drvdata *drvdata) >>       return 0; >>   } >>   +static ssize_t reset_store(struct device *dev, >> +                      struct device_attribute *attr, >> +                      const char *buf, >> +                      size_t size) > > Minor nit: alignment ? Could we have something like : > > static ssize_t reset_store(struct device *dev, >                struct device_attribute *attr, >                const char *buf, >                size_t size) > I will update this in the next patch series. Best, Tao > >> +{ >> +    int ret = 0; >> +    unsigned long val; >> +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); >> + >> +    ret = kstrtoul(buf, 10, &val); >> +    if (ret || val != 1) >> +        return -EINVAL; >> + >> +    spin_lock(&drvdata->spinlock); >> +    tpdm_reset_datasets(drvdata); >> +    spin_unlock(&drvdata->spinlock); >> + >> +    return size; >> +} >> +static DEVICE_ATTR_WO(reset); >> + >>   /* >>    * value 1: 64 bits test data >>    * value 2: 32 bits test data >> @@ -199,6 +220,7 @@ static ssize_t integration_test_store(struct >> device *dev, >>   static DEVICE_ATTR_WO(integration_test); >>     static struct attribute *tpdm_attrs[] = { >> +    &dev_attr_reset.attr, >>       &dev_attr_integration_test.attr, >>       NULL, >>   }; > > Suzuki >