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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-63c4949beedsm11980254a12.40.2025.10.22.08.27.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 22 Oct 2025 08:27:23 -0700 (PDT) Message-ID: Date: Wed, 22 Oct 2025 17:27:20 +0200 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/6] arm64: dts: qcom: qcs615: Add gpu and rgmu nodes To: Akhil P Oommen , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Jie Zhang References: <20251017-qcs615-spin-2-v1-0-0baa44f80905@oss.qualcomm.com> <20251017-qcs615-spin-2-v1-5-0baa44f80905@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20251017-qcs615-spin-2-v1-5-0baa44f80905@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE4MDAxNSBTYWx0ZWRfXxYv0eXBktlF4 mr1eaIUmdxli62mPMLa1TfTKlNxd+n6Ogm5zX5oXjadk0wWddba0qs26x3Vpou5YtAy//THLwmQ GRXT7teHD12xrVELukUVebQX3eyJ8N2oaXx8rFcqZO5yrIKClJvifFyxHtMoZIkgja/+YvSkAKM JCujDvMLs0x4EALSvv2NP4Rqs9vFWRQ/PvR5cxQm9OYm31pexNnk0WBsTwpSxJVWrayfquH82a/ avrFF0c6oHC6nC66T+HcI0lxXJOwg3zXdjTxFkR1cGPTFwFC2+wmkAd/GR9/HbEOxGB8TKXKSkw HcEHW8M8aFYf4gWH6FRQObPqOalVZ11u0WHETwRQGnH2jIZwM3ko+pLB1M+UXWbose3fsZxwO48 sVsdjsEWoWMA/hqic2X1WJBXUo2aZQ== X-Authority-Analysis: v=2.4 cv=bNUb4f+Z c=1 sm=1 tr=0 ts=68f8f7dd cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=e4uKRaRUJts94r9YfvAA:9 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: cMcK-qR4b-XbPORMzNvSrIrvUEiJJPvD X-Proofpoint-ORIG-GUID: cMcK-qR4b-XbPORMzNvSrIrvUEiJJPvD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-22_06,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 adultscore=0 spamscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510180015 On 10/17/25 7:08 PM, Akhil P Oommen wrote: > From: Jie Zhang > > Add gpu and rgmu nodes for qcs615 chipset. > > Signed-off-by: Jie Zhang > Signed-off-by: Akhil P Oommen > --- [...] > + gpu_zap_shader: zap-shader { > + memory-region = <&pil_gpu_mem>; > + }; > + > + gpu_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-845000000 { > + opp-hz = /bits/ 64 <845000000>; > + required-opps = <&rpmhpd_opp_turbo>; > + opp-peak-kBps = <7050000>; Are there speed bins? [...] > + rgmu: rgmu@506a000 { > + compatible = "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu"; > + reg = <0x0 0x0506a000 0x0 0x34000>; > + reg-names = "gmu"; > + > + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, > + <&gpucc GPU_CC_CXO_CLK>, > + <&gcc GCC_DDRSS_GPU_AXI_CLK>, > + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, > + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; > + clock-names = "gmu", > + "cxo", > + "axi", > + "memnoc", > + "smmu_vote"; > + > + power-domains = <&gpucc CX_GDSC>, > + <&gpucc GX_GDSC>, > + <&rpmhpd RPMHPD_CX>; > + power-domain-names = "cx", "gx", "vdd_cx"; I think the gpucc node should reference _CX directly instead, then genpd/opp should trickle the requirements up the chain > + > + interrupts = , > + ; > + interrupt-names = "oob", "gmu"; 1 a line, please lgtm otherwise Konrad