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Tue, 28 Jan 2025 07:12:31 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 50S7CUIv032677 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 28 Jan 2025 07:12:30 GMT Received: from [10.152.195.140] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 27 Jan 2025 23:12:23 -0800 Message-ID: Date: Tue, 28 Jan 2025 12:42:19 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/4] dt-bindings: clock: update interconnect cells for ipq5424 To: Krzysztof Kozlowski CC: , , , , , , , , , , , , , , , , , References: <20250125035920.2651972-1-quic_mmanikan@quicinc.com> <20250125035920.2651972-3-quic_mmanikan@quicinc.com> <20250127-amethyst-capybara-from-uranus-5e6bf4@krzk-bin> Content-Language: en-US From: Manikanta Mylavarapu In-Reply-To: <20250127-amethyst-capybara-from-uranus-5e6bf4@krzk-bin> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: HGZM0DjtlzhOkKvK2dHA0wC0vy-mq6IE X-Proofpoint-ORIG-GUID: HGZM0DjtlzhOkKvK2dHA0wC0vy-mq6IE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-28_02,2025-01-27_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 adultscore=0 mlxlogscore=999 phishscore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501280053 On 1/27/2025 12:57 PM, Krzysztof Kozlowski wrote: > On Sat, Jan 25, 2025 at 09:29:18AM +0530, Manikanta Mylavarapu wrote: >> Interconnect cells differ between the IPQ5332 and IPQ5424. >> Therefore, update the interconnect cells according to the SoC. > > Why do they differ? Why they cannot be the same? > Based on the comment received here [1], i updated interconnect cells to 2 to accommodate icc tags for IPQ5424. [1]: https://lore.kernel.org/linux-arm-msm/20250119124551.nl5272bz36ozvlqu@thinkpad/ I will update interconnect cells to 2 for IPQ5332 as well. >> >> Signed-off-by: Manikanta Mylavarapu >> --- >> .../devicetree/bindings/clock/qcom,ipq5332-gcc.yaml | 8 ++++++-- >> 1 file changed, 6 insertions(+), 2 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml >> index 1230183fc0a9..fac7922d2473 100644 >> --- a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml >> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml >> @@ -35,8 +35,6 @@ properties: >> - description: PCIE 2-lane PHY3 pipe clock source >> >> '#power-domain-cells': false >> - '#interconnect-cells': >> - const: 1 > > Properties are always defined top-level or in other schema. I will define it in top-level and initialize with 2. Thanks & Regards, Manikanta.