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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab772f84400sm87987366b.57.2025.02.06.03.42.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 06 Feb 2025 03:42:58 -0800 (PST) Message-ID: Date: Thu, 6 Feb 2025 12:42:56 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/2] arm64: dts: qcom: qcs615: Add clock nodes for multimedia clock To: Taniya Das , Konrad Dybcio , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250119-qcs615-mm-v2-dt-nodes-v2-0-c46ab4080989@quicinc.com> <20250119-qcs615-mm-v2-dt-nodes-v2-1-c46ab4080989@quicinc.com> <19a83d67-7e1a-495b-8dff-e1d2ba05b878@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: pyav5zXBOnxYEKd-7sSrS89OJN2OshU5 X-Proofpoint-GUID: pyav5zXBOnxYEKd-7sSrS89OJN2OshU5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-06_03,2025-02-05_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 spamscore=0 clxscore=1015 mlxlogscore=999 lowpriorityscore=0 bulkscore=0 impostorscore=0 phishscore=0 priorityscore=1501 malwarescore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502060097 On 4.02.2025 6:33 PM, Taniya Das wrote: > > > On 2/3/2025 7:44 PM, Konrad Dybcio wrote: >> On 19.01.2025 1:00 PM, Taniya Das wrote: >>> Add support for video, camera, display and gpu clock controller nodes >>> for QCS615 platform. >>> >>> Signed-off-by: Taniya Das >>> --- >>>   arch/arm64/boot/dts/qcom/qcs615.dtsi | 51 ++++++++++++++++++++++++++++++++++++ >>>   1 file changed, 51 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi >>> index f4abfad474ea62dea13d05eb874530947e1e8d3e..9d537019437c5202c4d398eecd0ce2a991083175 100644 >>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi >>> @@ -3,7 +3,11 @@ >>>    * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. >>>    */ >>>   +#include >>> +#include >>>   #include >>> +#include >>> +#include >>>   #include >>>   #include >>>   #include >>> @@ -1418,6 +1422,18 @@ data-pins { >>>               }; >>>           }; >>>   +        gpucc: clock-controller@5090000 { >>> +            compatible = "qcom,qcs615-gpucc"; >>> +            reg = <0 0x05090000 0 0x9000>; >>> + >>> +            clocks = <&rpmhcc RPMH_CXO_CLK>, >>> +                 <&gcc GPLL0>; >> >> This would normally be GCC_GPU_GPLL0_(DIV_)CLK_SRC, is this intentional? >> > > Yes, Konard, but on QCS615 GPLL0 is connected and not the GCC_GPU_GPLL0 sources. It looks like you're right.. if I'm looking in the right place, the _GPU_ ones are not connected anywhere.. It also seems like the reset state of the _GPU_ ones is OFF (as expected), should we remove them from the GCC driver to reduce confusion? Konrad