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Tue, 20 Jan 2026 12:27:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1768912035; bh=We6iPStU0ZFDOwTAL7qZlfBr4nmJKhgoqksa0yciLRc=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=n8aC/QvwvFFOP3yufXOJtOjJe/XstFlKJSXeyxXFVxtZom2AB4Wyb6Sl5K0vj96gN a/tWGLtAI1Py1Hkdlb6KS9EDHPNv9rpQgBiA2ePMF2dG/CYc6Dp2ibQCBVuMk44Met BWfvVLb2Hyrpnr8ep7OYAxDyUatZgk9eXGRCGNr3+mEZ1MRjZT57UO+x3DTPu2SHwn BumztqbzymIqqbgJaatoZItVouoryCjUwo+OKY0XnhoiFiD8agFXwb4Af8BTdwwIBm s8lo4pF5VEfABwAWlCxdY14qnkt8R0O9M+0TMUNqaFqWy7WHCdRLangR3t8mVSWK6j Lq22G3QPoulyg== Message-ID: <0d8ad41f-a2c4-4a4f-ac1f-68263648c4dc@kernel.org> Date: Tue, 20 Jan 2026 13:27:09 +0100 X-Mailing-List: linux-aspeed@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/3] pinctrl: aspeed: add G7(AST2700) SoC0 pinctrl support To: Billy Tsai , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Linus Walleij , Bartosz Golaszewski Cc: Andrew Jeffery , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org, linux-gpio@vger.kernel.org, bmc-sw@aspeedtech.com References: <20260120-upstream_pinctrl-v3-0-868fbf8413b5@aspeedtech.com> <20260120-upstream_pinctrl-v3-3-868fbf8413b5@aspeedtech.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 20/01/2026 12:43, Billy Tsai wrote: > Add pinctrl support for the SoC0 instance of the ASPEED AST2700. > > AST2700 consists of two interconnected SoC instances, each with its own > pinctrl register block. > > The SoC0 pinctrl hardware closely follows the design found in previous > ASPEED BMC generations, allowing the driver to build upon the common > ASPEED pinctrl infrastructure. > > Signed-off-by: Billy Tsai > --- > drivers/pinctrl/aspeed/Kconfig | 8 + > drivers/pinctrl/aspeed/Makefile | 1 + > drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c | 683 ++++++++++++++++++++++++ > 3 files changed, 692 insertions(+) > > diff --git a/drivers/pinctrl/aspeed/Kconfig b/drivers/pinctrl/aspeed/Kconfig > index 1a4e5b9ed471..16743091a139 100644 > --- a/drivers/pinctrl/aspeed/Kconfig > +++ b/drivers/pinctrl/aspeed/Kconfig > @@ -31,3 +31,11 @@ config PINCTRL_ASPEED_G6 > help > Say Y here to enable pin controller support for Aspeed's 6th > generation SoCs. GPIO is provided by a separate GPIO driver. > + > +config PINCTRL_ASPEED_G7 > + bool "Aspeed G7 SoC pin control" > + depends on (ARCH_ASPEED || COMPILE_TEST) && OF > + select PINCTRL_ASPEED > + help > + Say Y here to enable pin controller support for Aspeed's 7th > + generation SoCs. GPIO is provided by a separate GPIO driver. > diff --git a/drivers/pinctrl/aspeed/Makefile b/drivers/pinctrl/aspeed/Makefile > index db2a7600ae2b..cb2c81a69551 100644 > --- a/drivers/pinctrl/aspeed/Makefile > +++ b/drivers/pinctrl/aspeed/Makefile > @@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_ASPEED) += pinctrl-aspeed.o pinmux-aspeed.o > obj-$(CONFIG_PINCTRL_ASPEED_G4) += pinctrl-aspeed-g4.o > obj-$(CONFIG_PINCTRL_ASPEED_G5) += pinctrl-aspeed-g5.o > obj-$(CONFIG_PINCTRL_ASPEED_G6) += pinctrl-aspeed-g6.o > +obj-$(CONFIG_PINCTRL_ASPEED_G7) += pinctrl-aspeed-g7-soc0.o > \ No newline at end of file Do not introduce patch warnings. > diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c > new file mode 100644 > index 000000000000..c4e828c8839a > --- /dev/null > +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c > @@ -0,0 +1,683 @@ > +// SPDX-License-Identifier: GPL-2.0 > + ... > + > +static const struct aspeed_pinmux_ops aspeed_g7_soc0_ops = { > + .set = aspeed_g7_soc0_sig_expr_set, > +}; > + > +static struct aspeed_pinctrl_data aspeed_g7_soc0_pinctrl_data = { Look at your existing drivers - what is missing here and in other places? > + .pins = aspeed_g7_soc0_pins, > + .npins = ARRAY_SIZE(aspeed_g7_soc0_pins), > + .pinmux = { > + .ops = &aspeed_g7_soc0_ops, > + .groups = aspeed_g7_soc0_groups, > + .ngroups = ARRAY_SIZE(aspeed_g7_soc0_groups), > + .functions = aspeed_g7_soc0_functions, > + .nfunctions = ARRAY_SIZE(aspeed_g7_soc0_functions), > + }, > + .configs = aspeed_g7_soc0_configs, > + .nconfigs = ARRAY_SIZE(aspeed_g7_soc0_configs), > + .confmaps = aspeed_g7_soc0_pin_config_map, > + .nconfmaps = ARRAY_SIZE(aspeed_g7_soc0_pin_config_map), > +}; > + > +static int aspeed_g7_soc0_pinctrl_probe(struct platform_device *pdev) > +{ > + return aspeed_pinctrl_probe(pdev, &aspeed_g7_soc0_pinctrl_desc, > + &aspeed_g7_soc0_pinctrl_data); > +} > + > +static const struct of_device_id aspeed_g7_soc0_pinctrl_match[] = { > + { .compatible = "aspeed,ast2700-soc0-pinctrl" }, > + {} > +}; > +MODULE_DEVICE_TABLE(of, aspeed_g7_soc0_pinctrl_match); > + > +static struct platform_driver aspeed_g7_soc0_pinctrl_driver = { > + .probe = aspeed_g7_soc0_pinctrl_probe, > + .driver = { > + .name = "aspeed-g7-soc0-pinctrl", > + .of_match_table = aspeed_g7_soc0_pinctrl_match, > + .suppress_bind_attrs = true, > + }, > +}; > + > +static int __init aspeed_g7_soc0_pinctrl_init(void) > +{ > + return platform_driver_register(&aspeed_g7_soc0_pinctrl_driver); > +} > +arch_initcall(aspeed_g7_soc0_pinctrl_init); > Best regards, Krzysztof