From: Eddie James <eajames@linux.ibm.com>
To: linux-aspeed@lists.ozlabs.org
Subject: [PATCH 4/4] ARM: dts: aspeed: ast2600: Add SCU interrupt controllers
Date: Tue, 24 Sep 2019 11:14:32 -0500 [thread overview]
Message-ID: <1569341672-27632-5-git-send-email-eajames@linux.ibm.com> (raw)
In-Reply-To: <1569341672-27632-1-git-send-email-eajames@linux.ibm.com>
Add nodes for the interrupt controllers provided by the SCU.
Signed-off-by: Eddie James <eajames@linux.ibm.com>
---
arch/arm/boot/dts/aspeed-g6.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index 3a1422f..d89f1e6 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -159,6 +159,24 @@
compatible = "aspeed,ast2600-smpmem";
reg = <0x180 0x40>;
};
+
+ scu_ic0: interrupt-controller at 0 {
+ #interrupt-cells = <1>;
+ compatible = "aspeed,ast2600-scu-ic0";
+ reg = <0x560 0x4>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ };
+
+ scu_ic1: interrupt-controller at 1 {
+ #interrupt-cells = <1>;
+ compatible = "aspeed,ast2600-scu-ic1";
+ reg = <0x570 0x4>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ };
};
rng: hwrng at 1e6e2524 {
--
1.8.3.1
prev parent reply other threads:[~2019-09-24 16:14 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-24 16:14 [PATCH 0/4] irqchip: Add Aspeed SCU Interrupt Controller Eddie James
2019-09-24 16:14 ` [PATCH 1/4] dt-bindings: interrupt-controller: Add Aspeed SCU interrupt controller Eddie James
2019-09-24 16:14 ` [PATCH 2/4] irqchip: " Eddie James
2019-09-24 16:47 ` Marc Zyngier
2019-09-24 18:10 ` Eddie James
2019-09-24 16:14 ` [PATCH 3/4] ARM: dts: aspeed: ast2500: Add " Eddie James
2019-09-24 16:14 ` Eddie James [this message]
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