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Wed, 6 May 2026 01:31:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D7982C2BCB4; Wed, 6 May 2026 01:31:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778031083; bh=o2yy2Ww9i8w4gC0U+2YoW4VSEUxmrqIBx+Xo75LoX1c=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=epU1cA3klIDMZmbe9hL+8MnWKyObxZIooq0sRL5JIKYas2TmzTa13g2/yv9VuZORh XrHPPoRbcsnHfg4TqGwOgeCFlTeURJINvzMu2iCR2/YvAzu/GWB4k3bPYWJlGd57V2 4lu5djbXVU+F8w/WNmPawGsGNd3xbnUMQseazanwywzbZGsjjb/lWO/y7aAGXgFO7Y ry+7LBHj2eJf2Dxs0v3HVCA5uzHLHS0ffezdvR08F2//BiYMEAw5ISIBm22osmymHT mdSYe+cipA7QnicXft2QLiHe6IUR2ugzpVw+AmVHdnwVYw3WbNZ3+S2GXaZ+VCzx6I V2dWtoXGE99Rw== Date: Tue, 5 May 2026 20:31:20 -0500 From: "Rob Herring (Arm)" To: Billy Tsai Cc: Lee Jones , linux-arm-kernel@lists.infradead.org, Conor Dooley , Linus Walleij , Bartosz Golaszewski , linux-aspeed@lists.ozlabs.org, openbmc@lists.ozlabs.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-clk@vger.kernel.org, Andrew Jeffery , Joel Stanley , Andrew Jeffery , Ryan Chen , Krzysztof Kozlowski , devicetree@vger.kernel.org Subject: Re: [PATCH v8 2/3] dt-bindings: mfd: aspeed,ast2x00-scu: Describe AST2700 SCU0 Message-ID: <177803108003.262903.4940784340519563848.robh@kernel.org> References: <20260428-upstream_pinctrl-v8-0-eb8ef9ab0498@aspeedtech.com> <20260428-upstream_pinctrl-v8-2-eb8ef9ab0498@aspeedtech.com> X-Mailing-List: linux-aspeed@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260428-upstream_pinctrl-v8-2-eb8ef9ab0498@aspeedtech.com> On Tue, 28 Apr 2026 17:49:46 +0800, Billy Tsai wrote: > AST2700 consists of two interconnected SoC instances, each with its own > System Control Unit (SCU). The SCU0 provides pin control, interrupt > controllers, clocks, resets, and address-space mappings for the > Secondary and Tertiary Service Processors (SSP and TSP). > > Describe the SSP/TSP address mappings using the standard > memory-region and memory-region-names properties. > > Disallow legacy child nodes that are not present on AST2700, including > p2a-control and smp-memram. The latter is unnecessary as software can > access the scratch registers via the SCU syscon. > > Also allow the AST2700 SoC0 pin controller to be described as a child > node of the SCU0, and add an example illustrating the SCU0 layout, > including reserved-memory, interrupt controllers, and pinctrl. > > Signed-off-by: Billy Tsai > --- > .../bindings/mfd/aspeed,ast2x00-scu.yaml | 114 +++++++++++++++++++++ > 1 file changed, 114 insertions(+) > Reviewed-by: Rob Herring (Arm)