From mboxrd@z Thu Jan  1 00:00:00 1970
From: Stephen Boyd <sboyd@kernel.org>
Date: Fri, 08 Nov 2019 08:48:53 -0800
Subject: [PATCH v2 2/2] clk: ast2600: Add RMII RCLK gates for all four MACs
In-Reply-To: <20191010020725.3990-3-andrew@aj.id.au>
References: <20191010020725.3990-1-andrew@aj.id.au>
 <20191010020725.3990-3-andrew@aj.id.au>
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Quoting Andrew Jeffery (2019-10-09 19:07:25)
> RCLK is a fixed 50MHz clock derived from HPLL/HCLK that is described by a
> single gate for each MAC.
> 
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---

Applied to clk-next