From: Stephen Boyd <sboyd@kernel.org>
To: linux-aspeed@lists.ozlabs.org
Subject: [PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs
Date: Tue, 26 Nov 2019 10:01:17 -0800 [thread overview]
Message-ID: <20191126180118.C76792071A@mail.kernel.org> (raw)
In-Reply-To: <CACPK8XchwGdgE95jkdhwWbp0r+NHge7W3q6yQp-wzfxV3Kpajg@mail.gmail.com>
Quoting Joel Stanley (2019-11-25 16:59:19)
> Hi Stephen,
>
> On Thu, 10 Oct 2019 at 23:41, Joel Stanley <joel@jms.id.au> wrote:
> >
> > On Thu, 10 Oct 2019 at 02:06, Andrew Jeffery <andrew@aj.id.au> wrote:
> > >
> > > RCLK is a fixed 50MHz clock derived from HPLL that is described by a
> > > single gate for each MAC.
> > >
> > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> >
> > Reviewed-by: Joel Stanley <joel@jms.id.au>
>
> I noticed this one hasn't been applied to clk-next.
>
It's marked awaiting upstream in my UI. I think it was some patch that
might have come through your PR?
next prev parent reply other threads:[~2019-11-26 18:01 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-10 2:06 [PATCH v2 0/2] clk: aspeed: Expose RMII RCLK gate for MACs 1-2 on AST2500 Andrew Jeffery
2019-10-10 2:06 ` [PATCH v2 1/2] dt-bindings: clock: Add AST2500 RMII RCLK definitions Andrew Jeffery
2019-10-10 23:39 ` Joel Stanley
2019-10-11 17:01 ` Rob Herring
2019-10-10 2:06 ` [PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs Andrew Jeffery
2019-10-10 23:41 ` Joel Stanley
2019-11-26 0:59 ` Joel Stanley
2019-11-26 18:01 ` Stephen Boyd [this message]
2019-11-26 18:03 ` Stephen Boyd
2019-11-29 1:22 ` Joel Stanley
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