From mboxrd@z Thu Jan 1 00:00:00 1970 From: Delphine CC Chiu Date: Wed, 26 Jun 2024 17:07:29 +0800 Subject: [PATCH v9 13/26] ARM: dts: aspeed: yosemite4: Revise adc128d818 adc mode for yosemite4 schematic change In-Reply-To: <20240626090744.174351-1-Delphine_CC_Chiu@wiwynn.com> References: <20240626090744.174351-1-Delphine_CC_Chiu@wiwynn.com> Message-ID: <20240626090744.174351-14-Delphine_CC_Chiu@wiwynn.com> List-Id: To: linux-aspeed@lists.ozlabs.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Revise adc128d818 adc mode for yosemite4 schematic change Signed-off-by: Delphine CC Chiu --- .../boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts index 8f3bbdd1bbc5..0c7d85ff4360 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts @@ -1018,19 +1018,19 @@ &i2c14 { adc at 1d { compatible = "ti,adc128d818"; reg = <0x1d>; - ti,mode = /bits/ 8 <2>; + ti,mode = /bits/ 8 <1>; }; - adc at 35 { + adc at 36 { compatible = "ti,adc128d818"; - reg = <0x35>; - ti,mode = /bits/ 8 <2>; + reg = <0x36>; + ti,mode = /bits/ 8 <1>; }; adc at 37 { compatible = "ti,adc128d818"; reg = <0x37>; - ti,mode = /bits/ 8 <2>; + ti,mode = /bits/ 8 <1>; }; power-sensor at 40 { -- 2.25.1