From mboxrd@z Thu Jan 1 00:00:00 1970 From: Billy Tsai Date: Fri, 13 Sep 2024 15:43:19 +0800 Subject: [PATCH v3 0/6] Add Aspeed G7 gpio support Message-ID: <20240913074325.239390-1-billy_tsai@aspeedtech.com> List-Id: To: linux-aspeed@lists.ozlabs.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit The Aspeed 7th generation SoC features two GPIO controllers: one with 12 GPIO pins and another with 216 GPIO pins. The main difference from the previous generation is that the control logic has been updated to support per-pin control, allowing each pin to have its own 32-bit register for configuring value, direction, interrupt type, and more. This patch serial also add low-level operations (llops) to abstract the register access for GPIO registers and the coprocessor request/release in gpio-aspeed.c making it easier to extend the driver to support different hardware register layouts. Change since v2: - Correct minItems for gpio-line names - Remove the example for ast2700, because it???s the same as the AST2600 - Fix the sparse warning which is reported by the test robot - Remove the version and use the match data to replace it. - Add another two patches one for deferred probe one for flush write. Changes since v1: - Merge the gpio-aspeed-g7.c into the gpio-aspeed.c. - Create the llops in gpio-aspeed.c for flexibility. Billy Tsai (6): dt-bindings: gpio: aspeed,ast2400-gpio: Support ast2700 gpio: aspeed: Remove the name for bank array gpio: aspeed: Create llops to handle hardware access gpio: aspeed: Support G7 Aspeed gpio controller gpio: aspeed: Change the macro to support deferred probe gpio: aspeed: Add the flush write to ensure the write complete. .../bindings/gpio/aspeed,ast2400-gpio.yaml | 19 +- drivers/gpio/gpio-aspeed.c | 498 +++++++++++------- 2 files changed, 313 insertions(+), 204 deletions(-) -- 2.25.1