* [PATCH v1 0/3] Revise Meta (Facebook) Minerva BMC (AST2600)
@ 2024-09-24 14:02 Yang Chen
2024-09-24 14:02 ` [PATCH v1 1/3] ARM: dts: aspeed: minerva: Revise the SGPIO line name Yang Chen
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Yang Chen @ 2024-09-24 14:02 UTC (permalink / raw)
To: linux-aspeed
Revise linux device tree entry related to Meta (Facebook) Minerva specific
devices connected to BMC (AST2600) SoC.
Yang Chen (3):
ARM: dts: aspeed: minerva: Revise the SGPIO line name
ARM: dts: aspeed: minerva: change the i2c mux number for FCBs
ARM: dts: aspeed: minerva: add fru device for other blades
.../aspeed/aspeed-bmc-facebook-minerva.dts | 475 +++++++++++++++---
1 file changed, 405 insertions(+), 70 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v1 1/3] ARM: dts: aspeed: minerva: Revise the SGPIO line name
2024-09-24 14:02 [PATCH v1 0/3] Revise Meta (Facebook) Minerva BMC (AST2600) Yang Chen
@ 2024-09-24 14:02 ` Yang Chen
2024-09-24 14:02 ` [PATCH v1 2/3] ARM: dts: aspeed: minerva: change the i2c mux number for FCBs Yang Chen
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Yang Chen @ 2024-09-24 14:02 UTC (permalink / raw)
To: linux-aspeed
Modify the SGPIO line names sent from the CMM CPLD in the DVT version and
map the blade and FCB numbers to match the silkscreen labels on the rack as
follows:
1. Change the compute blade numbering from 0-15 to 1-16.
2. Change the network blade numbering from 0-5 to 1-6.
3. Update the FCB numbering from TOP0/1, MID0/1, and BOT0/1 to FCB1-6.
4. Revise the SGPIO line name for DVT changed.
Signed-off-by: Yang Chen <yangchen.openbmc@gmail.com>
---
.../aspeed/aspeed-bmc-facebook-minerva.dts | 110 +++++++++---------
1 file changed, 55 insertions(+), 55 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts
index 41e2246cfbd1..38eb42aaa98b 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts
@@ -627,7 +627,6 @@ &sgpiom0 {
gpio-line-names =
/*"input pin","output pin"*/
/*A0 - A7*/
- "PRSNT_MTIA_BLADE0_N","PWREN_MTIA_BLADE0_EN_N",
"PRSNT_MTIA_BLADE1_N","PWREN_MTIA_BLADE1_EN_N",
"PRSNT_MTIA_BLADE2_N","PWREN_MTIA_BLADE2_EN_N",
"PRSNT_MTIA_BLADE3_N","PWREN_MTIA_BLADE3_EN_N",
@@ -635,8 +634,8 @@ &sgpiom0 {
"PRSNT_MTIA_BLADE5_N","PWREN_MTIA_BLADE5_EN_N",
"PRSNT_MTIA_BLADE6_N","PWREN_MTIA_BLADE6_EN_N",
"PRSNT_MTIA_BLADE7_N","PWREN_MTIA_BLADE7_EN_N",
- /*B0 - B7*/
"PRSNT_MTIA_BLADE8_N","PWREN_MTIA_BLADE8_EN_N",
+ /*B0 - B7*/
"PRSNT_MTIA_BLADE9_N","PWREN_MTIA_BLADE9_EN_N",
"PRSNT_MTIA_BLADE10_N","PWREN_MTIA_BLADE10_EN_N",
"PRSNT_MTIA_BLADE11_N","PWREN_MTIA_BLADE11_EN_N",
@@ -644,80 +643,80 @@ &sgpiom0 {
"PRSNT_MTIA_BLADE13_N","PWREN_MTIA_BLADE13_EN_N",
"PRSNT_MTIA_BLADE14_N","PWREN_MTIA_BLADE14_EN_N",
"PRSNT_MTIA_BLADE15_N","PWREN_MTIA_BLADE15_EN_N",
+ "PRSNT_MTIA_BLADE16_N","PWREN_MTIA_BLADE16_EN_N",
/*C0 - C7*/
- "PRSNT_NW_BLADE0_N","PWREN_NW_BLADE0_EN_N",
"PRSNT_NW_BLADE1_N","PWREN_NW_BLADE1_EN_N",
"PRSNT_NW_BLADE2_N","PWREN_NW_BLADE2_EN_N",
"PRSNT_NW_BLADE3_N","PWREN_NW_BLADE3_EN_N",
"PRSNT_NW_BLADE4_N","PWREN_NW_BLADE4_EN_N",
"PRSNT_NW_BLADE5_N","PWREN_NW_BLADE5_EN_N",
- "PRSNT_FCB_TOP_0_N","PWREN_MTIA_BLADE0_HSC_EN_N",
- "PRSNT_FCB_TOP_1_N","PWREN_MTIA_BLADE1_HSC_EN_N",
+ "PRSNT_NW_BLADE6_N","PWREN_NW_BLADE6_EN_N",
+ "PRSNT_FCB_1_N","PWREN_MTIA_BLADE1_HSC_EN_N",
+ "PRSNT_FCB_2_N","PWREN_MTIA_BLADE2_HSC_EN_N",
/*D0 - D7*/
- "PRSNT_FCB_MIDDLE_0_N","PWREN_MTIA_BLADE2_HSC_EN_N",
- "PRSNT_FCB_MIDDLE_1_N","PWREN_MTIA_BLADE3_HSC_EN_N",
- "PRSNT_FCB_BOTTOM_1_N","PWREN_MTIA_BLADE4_HSC_EN_N",
- "PRSNT_FCB_BOTTOM_0_N","PWREN_MTIA_BLADE5_HSC_EN_N",
- "PWRGD_MTIA_BLADE0_PWROK_N","PWREN_MTIA_BLADE6_HSC_EN_N",
+ "PRSNT_FCB_3_N","PWREN_MTIA_BLADE3_HSC_EN_N",
+ "PRSNT_FCB_4_N","PWREN_MTIA_BLADE4_HSC_EN_N",
+ "PRSNT_FCB_6_N","PWREN_MTIA_BLADE5_HSC_EN_N",
+ "PRSNT_FCB_5_N","PWREN_MTIA_BLADE6_HSC_EN_N",
"PWRGD_MTIA_BLADE1_PWROK_N","PWREN_MTIA_BLADE7_HSC_EN_N",
"PWRGD_MTIA_BLADE2_PWROK_N","PWREN_MTIA_BLADE8_HSC_EN_N",
"PWRGD_MTIA_BLADE3_PWROK_N","PWREN_MTIA_BLADE9_HSC_EN_N",
- /*E0 - E7*/
"PWRGD_MTIA_BLADE4_PWROK_N","PWREN_MTIA_BLADE10_HSC_EN_N",
+ /*E0 - E7*/
"PWRGD_MTIA_BLADE5_PWROK_N","PWREN_MTIA_BLADE11_HSC_EN_N",
"PWRGD_MTIA_BLADE6_PWROK_N","PWREN_MTIA_BLADE12_HSC_EN_N",
"PWRGD_MTIA_BLADE7_PWROK_N","PWREN_MTIA_BLADE13_HSC_EN_N",
"PWRGD_MTIA_BLADE8_PWROK_N","PWREN_MTIA_BLADE14_HSC_EN_N",
"PWRGD_MTIA_BLADE9_PWROK_N","PWREN_MTIA_BLADE15_HSC_EN_N",
- "PWRGD_MTIA_BLADE10_PWROK_N","PWREN_NW_BLADE0_HSC_EN_N",
+ "PWRGD_MTIA_BLADE10_PWROK_N","PWREN_MTIA_BLADE16_HSC_EN_N",
"PWRGD_MTIA_BLADE11_PWROK_N","PWREN_NW_BLADE1_HSC_EN_N",
- /*F0 - F7*/
"PWRGD_MTIA_BLADE12_PWROK_N","PWREN_NW_BLADE2_HSC_EN_N",
+ /*F0 - F7*/
"PWRGD_MTIA_BLADE13_PWROK_N","PWREN_NW_BLADE3_HSC_EN_N",
"PWRGD_MTIA_BLADE14_PWROK_N","PWREN_NW_BLADE4_HSC_EN_N",
"PWRGD_MTIA_BLADE15_PWROK_N","PWREN_NW_BLADE5_HSC_EN_N",
- "PWRGD_NW_BLADE0_PWROK_N","PWREN_FCB_TOP_0_EN_N",
- "PWRGD_NW_BLADE1_PWROK_N","PWREN_FCB_TOP_1_EN_N",
- "PWRGD_NW_BLADE2_PWROK_N","PWREN_FCB_MIDDLE_0_EN_N",
- "PWRGD_NW_BLADE3_PWROK_N","PWREN_FCB_MIDDLE_1_EN_N",
+ "PWRGD_MTIA_BLADE16_PWROK_N","PWREN_NW_BLADE6_HSC_EN_N",
+ "PWRGD_NW_BLADE1_PWROK_N","PWREN_SGPIO_FCB_2_EN_N",
+ "PWRGD_NW_BLADE2_PWROK_N","PWREN_SGPIO_FCB_1_EN_N",
+ "PWRGD_NW_BLADE3_PWROK_N","PWREN_SGPIO_FCB_4_EN_N",
+ "PWRGD_NW_BLADE4_PWROK_N","PWREN_SGPIO_FCB_3_EN_N",
/*G0 - G7*/
- "PWRGD_NW_BLADE4_PWROK_N","PWREN_FCB_BOTTOM_1_EN_N",
- "PWRGD_NW_BLADE5_PWROK_N","PWREN_FCB_BOTTOM_0_EN_N",
- "PWRGD_FCB_TOP_0_PWROK_N","FM_CMM_AC_CYCLE_N",
- "PWRGD_FCB_TOP_1_PWROK_N","MGMT_SFP_TX_DIS",
- "PWRGD_FCB_MIDDLE_0_PWROK_N","FM_MDIO_SW_SEL",
- "PWRGD_FCB_MIDDLE_1_PWROK_N","FM_P24V_SMPWR_EN",
- "PWRGD_FCB_BOTTOM_1_PWROK_N","",
- "PWRGD_FCB_BOTTOM_0_PWROK_N","",
+ "PWRGD_NW_BLADE5_PWROK_N","PWREN_SGPIO_FCB_5_EN_N",
+ "PWRGD_NW_BLADE6_PWROK_N","PWREN_SGPIO_FCB_6_EN_N",
+ "PWRGD_FCB_1","FM_BMC_RST_RTCRST_R",
+ "PWRGD_FCB_2","",
+ "PWRGD_FCB_3","FM_MDIO_SW_SEL",
+ "PWRGD_FCB_4","FM_P24V_SMPWR_EN",
+ "PWRGD_FCB_6","",
+ "PWRGD_FCB_5","",
/*H0 - H7*/
- "LEAK_DETECT_MTIA_BLADE0_N","",
"LEAK_DETECT_MTIA_BLADE1_N","",
"LEAK_DETECT_MTIA_BLADE2_N","",
"LEAK_DETECT_MTIA_BLADE3_N","",
"LEAK_DETECT_MTIA_BLADE4_N","",
"LEAK_DETECT_MTIA_BLADE5_N","",
"LEAK_DETECT_MTIA_BLADE6_N","",
- "LEAK_DETECT_MTIA_BLADE7_N","",
+ "LEAK_DETECT_MTIA_BLADE7_N","ERR_INJECT_CMM_PWR_FAIL_N",
+ "LEAK_DETECT_MTIA_BLADE8_N","",
/*I0 - I7*/
- "LEAK_DETECT_MTIA_BLADE8_N","RST_I2CRST_FCB_BOTTOM_1_N",
- "LEAK_DETECT_MTIA_BLADE9_N","RST_I2CRST_FCB_BOTTOM_0_N",
- "LEAK_DETECT_MTIA_BLADE10_N","RST_I2CRST_FCB_MIDDLE_0_N",
- "LEAK_DETECT_MTIA_BLADE11_N","RST_I2CRST_FCB_MIDDLE_1_N",
- "LEAK_DETECT_MTIA_BLADE12_N","RST_I2CRST_FCB_TOP_0_N",
- "LEAK_DETECT_MTIA_BLADE13_N","RST_I2CRST_FCB_TOP_1_N",
- "LEAK_DETECT_MTIA_BLADE14_N","BMC_READY",
- "LEAK_DETECT_MTIA_BLADE15_N","FM_88E6393X_BIN_UPDATE_EN_N",
+ "LEAK_DETECT_MTIA_BLADE9_N","RST_I2CRST_FCB_5_N",
+ "LEAK_DETECT_MTIA_BLADE10_N","RST_I2CRST_FCB_6_N",
+ "LEAK_DETECT_MTIA_BLADE11_N","RST_I2CRST_FCB_4_N",
+ "LEAK_DETECT_MTIA_BLADE12_N","RST_I2CRST_FCB_3_N",
+ "LEAK_DETECT_MTIA_BLADE13_N","RST_I2CRST_FCB_2_N",
+ "LEAK_DETECT_MTIA_BLADE14_N","RST_I2CRST_FCB_1_N",
+ "LEAK_DETECT_MTIA_BLADE15_N","BMC_READY",
+ "LEAK_DETECT_MTIA_BLADE16_N","FM_88E6393X_BIN_UPDATE_EN_N",
/*J0 - J7*/
- "LEAK_DETECT_NW_BLADE0_N","WATER_VALVE_CLOSED_N",
- "LEAK_DETECT_NW_BLADE1_N","",
+ "LEAK_DETECT_NW_BLADE1_N","WATER_VALVE_CLOSED_N",
"LEAK_DETECT_NW_BLADE2_N","",
"LEAK_DETECT_NW_BLADE3_N","",
"LEAK_DETECT_NW_BLADE4_N","",
"LEAK_DETECT_NW_BLADE5_N","",
- "PWRGD_MTIA_BLADE0_HSC_PWROK_N","",
+ "LEAK_DETECT_NW_BLADE6_N","",
"PWRGD_MTIA_BLADE1_HSC_PWROK_N","",
- /*K0 - K7*/
"PWRGD_MTIA_BLADE2_HSC_PWROK_N","",
+ /*K0 - K7*/
"PWRGD_MTIA_BLADE3_HSC_PWROK_N","",
"PWRGD_MTIA_BLADE4_HSC_PWROK_N","",
"PWRGD_MTIA_BLADE5_HSC_PWROK_N","",
@@ -725,49 +724,50 @@ &sgpiom0 {
"PWRGD_MTIA_BLADE7_HSC_PWROK_N","",
"PWRGD_MTIA_BLADE8_HSC_PWROK_N","",
"PWRGD_MTIA_BLADE9_HSC_PWROK_N","",
- /*L0 - L7*/
"PWRGD_MTIA_BLADE10_HSC_PWROK_N","",
+ /*L0 - L7*/
"PWRGD_MTIA_BLADE11_HSC_PWROK_N","",
"PWRGD_MTIA_BLADE12_HSC_PWROK_N","",
"PWRGD_MTIA_BLADE13_HSC_PWROK_N","",
"PWRGD_MTIA_BLADE14_HSC_PWROK_N","",
"PWRGD_MTIA_BLADE15_HSC_PWROK_N","",
- "PWRGD_NW_BLADE0_HSC_PWROK_N","",
+ "PWRGD_MTIA_BLADE16_HSC_PWROK_N","",
"PWRGD_NW_BLADE1_HSC_PWROK_N","",
- /*M0 - M7*/
"PWRGD_NW_BLADE2_HSC_PWROK_N","",
+ /*M0 - M7*/
"PWRGD_NW_BLADE3_HSC_PWROK_N","",
"PWRGD_NW_BLADE4_HSC_PWROK_N","",
"PWRGD_NW_BLADE5_HSC_PWROK_N","",
+ "PWRGD_NW_BLADE6_HSC_PWROK_N","",
"RPU_READY","",
"IT_GEAR_RPU_LINK_N","",
"IT_GEAR_LEAK","",
"WATER_VALVE_CLOSED_N","",
/*N0 - N7*/
- "VALVE_STS0","",
- "VALVE_STS1","",
- "PCA9555_IRQ0_N","",
+ "VALVE_STATUS_0","",
+ "VALVE_STATUS_1","",
"PCA9555_IRQ1_N","",
+ "PCA9555_IRQ2_N","",
"CR_TOGGLE_BOOT_N","",
- "IRQ_FCB_TOP0_N","",
- "IRQ_FCB_TOP1_N","",
+ "IRQ_FCB_1_N","",
+ "IRQ_FCB_2_N","",
"CMM_CABLE_CARTRIDGE_PRSNT_BOT_N","",
/*O0 - O7*/
"CMM_CABLE_CARTRIDGE_PRSNT_TOP_N","",
"BOT_BCB_CABLE_PRSNT_N","",
"TOP_BCB_CABLE_PRSNT_N","",
- "IRQ_FCB_MID0_N","",
- "IRQ_FCB_MID1_N","",
+ "IRQ_FCB_3_N","",
+ "IRQ_FCB_4_N","",
"CHASSIS_LEAK0_DETECT_N","",
"CHASSIS_LEAK1_DETECT_N","",
- "VALVE_RMON_A_1","",
+ "PCA9555_IRQ3_N","",
/*P0 - P7*/
- "VALVE_RMON_A_2","",
- "VALVE_RMON_B_1","",
- "VALVE_RMON_B_2","",
+ "PCA9555_IRQ4_N","",
+ "PCA9555_IRQ5_N","",
+ "CMM_AC_PWR_BTN_N","",
"RPU_READY_SPARE","",
"IT_GEAR_LEAK_SPARE","",
"IT_GEAR_RPU_LINK_SPARE_N","",
- "IRQ_FCB_BOT0_N","",
- "IRQ_FCB_BOT0_N","";
+ "IRQ_FCB_6_N","",
+ "IRQ_FCB_5_N","";
};
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v1 2/3] ARM: dts: aspeed: minerva: change the i2c mux number for FCBs
2024-09-24 14:02 [PATCH v1 0/3] Revise Meta (Facebook) Minerva BMC (AST2600) Yang Chen
2024-09-24 14:02 ` [PATCH v1 1/3] ARM: dts: aspeed: minerva: Revise the SGPIO line name Yang Chen
@ 2024-09-24 14:02 ` Yang Chen
2024-09-24 14:02 ` [PATCH v1 3/3] ARM: dts: aspeed: minerva: add fru device for other blades Yang Chen
2024-09-25 0:44 ` [PATCH v1 0/3] Revise Meta (Facebook) Minerva BMC (AST2600) Andrew Jeffery
3 siblings, 0 replies; 5+ messages in thread
From: Yang Chen @ 2024-09-24 14:02 UTC (permalink / raw)
To: linux-aspeed
Change the i2c mux channel to match the correct fan board location.
Signed-off-by: Yang Chen <yangchen.openbmc@gmail.com>
---
.../aspeed/aspeed-bmc-facebook-minerva.dts | 31 ++++++++++---------
1 file changed, 16 insertions(+), 15 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts
index 38eb42aaa98b..c915db28a806 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts
@@ -213,10 +213,11 @@ i2c-mux at 77 {
#size-cells = <0>;
i2c-mux-idle-disconnect;
- imux16: i2c at 0 {
+ // FCB 1
+ imux16: i2c at 1 {
#address-cells = <1>;
#size-cells = <0>;
- reg = <0>;
+ reg = <1>;
eeprom at 50 {
compatible = "atmel,24c128";
@@ -259,11 +260,11 @@ temperature-sensor at 4b {
reg = <0x4b>;
};
};
-
- imux17: i2c at 1 {
+ // FCB 2
+ imux17: i2c at 0 {
#address-cells = <1>;
#size-cells = <0>;
- reg = <1>;
+ reg = <0>;
eeprom at 50 {
compatible = "atmel,24c128";
@@ -306,11 +307,11 @@ temperature-sensor at 4b {
reg = <0x4b>;
};
};
-
- imux18: i2c at 2 {
+ // FCB 3
+ imux18: i2c at 3 {
#address-cells = <1>;
#size-cells = <0>;
- reg = <2>;
+ reg = <3>;
eeprom at 50 {
compatible = "atmel,24c128";
@@ -353,11 +354,11 @@ temperature-sensor at 4b {
reg = <0x4b>;
};
};
-
- imux19: i2c at 3 {
+ // FCB 4
+ imux19: i2c at 2 {
#address-cells = <1>;
#size-cells = <0>;
- reg = <3>;
+ reg = <2>;
eeprom at 50 {
compatible = "atmel,24c128";
@@ -400,8 +401,8 @@ temperature-sensor at 4b {
reg = <0x4b>;
};
};
-
- imux20: i2c at 5 {
+ // FCB 5
+ imux20: i2c at 4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
@@ -446,8 +447,8 @@ temperature-sensor at 4b {
reg = <0x4b>;
};
};
-
- imux21: i2c at 4 {
+ // FCB 6
+ imux21: i2c at 5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v1 3/3] ARM: dts: aspeed: minerva: add fru device for other blades
2024-09-24 14:02 [PATCH v1 0/3] Revise Meta (Facebook) Minerva BMC (AST2600) Yang Chen
2024-09-24 14:02 ` [PATCH v1 1/3] ARM: dts: aspeed: minerva: Revise the SGPIO line name Yang Chen
2024-09-24 14:02 ` [PATCH v1 2/3] ARM: dts: aspeed: minerva: change the i2c mux number for FCBs Yang Chen
@ 2024-09-24 14:02 ` Yang Chen
2024-09-25 0:44 ` [PATCH v1 0/3] Revise Meta (Facebook) Minerva BMC (AST2600) Andrew Jeffery
3 siblings, 0 replies; 5+ messages in thread
From: Yang Chen @ 2024-09-24 14:02 UTC (permalink / raw)
To: linux-aspeed
The Minerva platform has 16 compute blades and 6 network blades, each with
an EEPROM that can be operated by the CMM. This commit adds support for
each FRU.
Signed-off-by: Yang Chen <yangchen.openbmc@gmail.com>
---
.../aspeed/aspeed-bmc-facebook-minerva.dts | 334 ++++++++++++++++++
1 file changed, 334 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts
index c915db28a806..468a33f50ef2 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts
@@ -23,6 +23,32 @@ aliases {
i2c19 = &imux19;
i2c20 = &imux20;
i2c21 = &imux21;
+ i2c22 = &imux22;
+ i2c23 = &imux23;
+ i2c24 = &imux24;
+ i2c25 = &imux25;
+ i2c26 = &imux26;
+ i2c27 = &imux27;
+ i2c28 = &imux28;
+ i2c29 = &imux29;
+ i2c30 = &imux30;
+ i2c31 = &imux31;
+ i2c32 = &imux32;
+ i2c33 = &imux33;
+ i2c34 = &imux34;
+ i2c35 = &imux35;
+ i2c36 = &imux36;
+ i2c37 = &imux37;
+ i2c38 = &imux38;
+ i2c39 = &imux39;
+ i2c40 = &imux40;
+ i2c41 = &imux41;
+ i2c42 = &imux42;
+ i2c43 = &imux43;
+ i2c44 = &imux44;
+ i2c45 = &imux45;
+ i2c46 = &imux46;
+ i2c47 = &imux47;
spi1 = &spi_gpio;
};
@@ -493,23 +519,239 @@ temperature-sensor at 4b {
reg = <0x4b>;
};
};
+
+ imux22: i2c at 6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+
+ imux23: i2c at 7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
};
};
&i2c3 {
status = "okay";
+
+ i2c-mux at 72 {
+ compatible = "nxp,pca9545";
+ reg = <0x72>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ imux24: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ eeprom at 50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+ };
+
+ imux25: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ eeprom at 50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+ };
+
+ imux26: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ eeprom at 50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+ };
+
+ imux27: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ eeprom at 50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+ };
+ };
};
&i2c4 {
status = "okay";
+
+ i2c-mux at 72 {
+ compatible = "nxp,pca9545";
+ reg = <0x72>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ imux28: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ eeprom at 50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+ };
+
+ imux29: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ eeprom at 50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+ };
+
+ imux30: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ eeprom at 50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+ };
+
+ imux31: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ eeprom at 50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+ };
+ };
};
&i2c5 {
status = "okay";
+
+ i2c-mux at 72 {
+ compatible = "nxp,pca9545";
+ reg = <0x72>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ imux32: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ eeprom at 50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+ };
+
+ imux33: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ eeprom at 50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+ };
+
+ imux34: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ eeprom at 50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+ };
+
+ imux35: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ eeprom at 50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+ };
+ };
};
&i2c6 {
status = "okay";
+
+ i2c-mux at 72 {
+ compatible = "nxp,pca9545";
+ reg = <0x72>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ imux36: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ eeprom at 50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+ };
+
+ imux37: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ eeprom at 50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+ };
+
+ imux38: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ eeprom at 50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+ };
+
+ imux39: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ eeprom at 50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+ };
+ };
};
&i2c7 {
@@ -536,10 +778,102 @@ rtc at 51 {
&i2c12 {
status = "okay";
+
+ i2c-mux at 70 {
+ compatible = "nxp,pca9545";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ imux40: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ eeprom at 50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+ };
+
+ imux41: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ eeprom at 50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+ };
+
+ imux42: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ eeprom at 50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+ };
+
+ imux43: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
};
&i2c13 {
status = "okay";
+
+ i2c-mux at 70 {
+ compatible = "nxp,pca9545";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ imux44: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ eeprom at 50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+ };
+
+ imux45: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ eeprom at 50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+ };
+
+ imux46: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ eeprom at 50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+ };
+
+ imux47: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
};
&i2c14 {
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v1 0/3] Revise Meta (Facebook) Minerva BMC (AST2600)
2024-09-24 14:02 [PATCH v1 0/3] Revise Meta (Facebook) Minerva BMC (AST2600) Yang Chen
` (2 preceding siblings ...)
2024-09-24 14:02 ` [PATCH v1 3/3] ARM: dts: aspeed: minerva: add fru device for other blades Yang Chen
@ 2024-09-25 0:44 ` Andrew Jeffery
3 siblings, 0 replies; 5+ messages in thread
From: Andrew Jeffery @ 2024-09-25 0:44 UTC (permalink / raw)
To: linux-aspeed
On Tue, 24 Sep 2024 22:02:12 +0800, Yang Chen wrote:
> Revise linux device tree entry related to Meta (Facebook) Minerva specific
> devices connected to BMC (AST2600) SoC.
>
> Yang Chen (3):
> ARM: dts: aspeed: minerva: Revise the SGPIO line name
> ARM: dts: aspeed: minerva: change the i2c mux number for FCBs
> ARM: dts: aspeed: minerva: add fru device for other blades
>
> [...]
Thanks, I've applied this to be picked up through the BMC tree.
--
Andrew Jeffery <andrew@codeconstruct.com.au>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2024-09-25 0:44 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-09-24 14:02 [PATCH v1 0/3] Revise Meta (Facebook) Minerva BMC (AST2600) Yang Chen
2024-09-24 14:02 ` [PATCH v1 1/3] ARM: dts: aspeed: minerva: Revise the SGPIO line name Yang Chen
2024-09-24 14:02 ` [PATCH v1 2/3] ARM: dts: aspeed: minerva: change the i2c mux number for FCBs Yang Chen
2024-09-24 14:02 ` [PATCH v1 3/3] ARM: dts: aspeed: minerva: add fru device for other blades Yang Chen
2024-09-25 0:44 ` [PATCH v1 0/3] Revise Meta (Facebook) Minerva BMC (AST2600) Andrew Jeffery
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