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From: Kevin Chen <kevin_chen@aspeedtech.com>
To: <lee@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,
	<conor+dt@kernel.org>, <joel@jms.id.au>,
	<andrew@codeconstruct.com.au>, <derek.kiernan@amd.com>,
	<dragan.cvetic@amd.com>, <arnd@arndb.de>,
	<gregkh@linuxfoundation.org>, <devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-aspeed@lists.ozlabs.org>, <linux-kernel@vger.kernel.org>
Cc: Kevin Chen <kevin_chen@aspeedtech.com>
Subject: [PATCH v4 1/3] dt-binding: aspeed: Add LPC PCC controller
Date: Fri, 14 Mar 2025 19:21:11 +0800	[thread overview]
Message-ID: <20250314112113.953238-2-kevin_chen@aspeedtech.com> (raw)
In-Reply-To: <20250314112113.953238-1-kevin_chen@aspeedtech.com>

Add dt-bindings for Aspeed for Aspeed LPC POST code capture controller.

Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
---
 .../devicetree/bindings/mfd/aspeed-lpc.yaml   | 38 +++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
index 5dfe77aca167..178c151a19ba 100644
--- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
+++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
@@ -149,6 +149,37 @@ patternProperties:
       - interrupts
       - snoop-ports
 
+  "^lpc-pcc@[0-9a-f]+$":
+    type: object
+    additionalProperties: false
+
+    description:
+      The LPC pcc interface allows the BMC to listen on and record the data
+      bytes written by the Host to the targeted LPC I/O pots.
+
+    properties:
+      compatible:
+        items:
+          - enum:
+              - aspeed,ast2600-lpc-pcc
+
+      reg:
+        maxItems: 1
+
+      interrupts:
+        maxItems: 1
+
+      pcc-ports:
+        $ref: /schemas/types.yaml#/definitions/uint32-array
+        description:
+          As a device handshake with a host using the port-mmaped I/O in x86
+          architecture, need to handle specific which port I/O address for use.
+
+    required:
+      - compatible
+      - interrupts
+      - pcc-ports
+
   "^uart-routing@[0-9a-f]+$":
     $ref: /schemas/soc/aspeed/uart-routing.yaml#
     description: The UART routing control under LPC register space
@@ -176,6 +207,13 @@ examples:
         #size-cells = <1>;
         ranges = <0x0 0x1e789000 0x1000>;
 
+        lpc_pcc: lpc-pcc@0 {
+            compatible = "aspeed,ast2600-lpc-pcc";
+            reg = <0x0 0x140>;
+            interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+            pcc-ports = <0x80>;
+        };
+
         lpc_ctrl: lpc-ctrl@80 {
             compatible = "aspeed,ast2600-lpc-ctrl";
             reg = <0x80 0x80>;
-- 
2.34.1



  reply	other threads:[~2025-03-14 11:21 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-14 11:21 [PATCH v4 0/3] Add AST2600 LPC PCC support Kevin Chen
2025-03-14 11:21 ` Kevin Chen [this message]
2025-03-17  9:12   ` [PATCH v4 1/3] dt-binding: aspeed: Add LPC PCC controller Krzysztof Kozlowski
2025-03-14 11:21 ` [PATCH v4 2/3] ARM: dts: aspeed-g6: Add AST2600 LPC PCC support Kevin Chen
2025-03-17  9:13   ` Krzysztof Kozlowski
2025-03-14 11:21 ` [PATCH v4 3/3] soc: aspeed: lpc-pcc: Add PCC controller support Kevin Chen
2025-03-18  0:42   ` Andrew Jeffery

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