From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 74B11C61DB2 for ; Fri, 13 Jun 2025 05:11:12 +0000 (UTC) Received: from boromir.ozlabs.org (localhost [127.0.0.1]) by lists.ozlabs.org (Postfix) with ESMTP id 4bJSCy6Dxgz30Qb; Fri, 13 Jun 2025 15:11:10 +1000 (AEST) Authentication-Results: lists.ozlabs.org; arc=none smtp.remote-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=lists.ozlabs.org; s=201707; t=1749785425; cv=none; b=nKnOwF6cBY+qak4qSjtX9iNjtShyN62MGE2TgP0FrdMAb9xYRTprca50OzYnCWRYLzBIC1DKRJAw3v9f0GoyzIOdZO5QWHokV0JEPbCmTF32Mg38SHc6R+DZ+9FA57QKDKQluHXuXeVakoiQPPQG4YkMhVE6Y+nZSccBOreZkuBtuzsprEIclTmnF4NJdNBaZcAMl0AHGnw9/utyh29jR8ACeUA9LMw0FfXlOxTyVBo3BfBO0lYycTRQ/DZMfWIJy+eaf+NtlUE8eIuWi7Iu8yQU0FfMvyOPMJrzQmtLYnsjyP7TPjfZIicMqe5BXd8BBnfXZ94HIyChdFOwfEUIVw== ARC-Message-Signature: i=1; a=rsa-sha256; d=lists.ozlabs.org; s=201707; t=1749785425; c=relaxed/relaxed; bh=cm0i6X2961Akf+Ls+i0/k+ZjUPURiX4Nw6tGye1S4Nw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cEdnYRexYf8JlCumgH2Oa23oYW/RR5ChX/BjuDBlMCzEQvvHNkWLuksobNIDvMxyDIL2GukvifWD29e0di7q8sEnJLsXA+2Tc+ICsJEVQ9BuIcOWNd5AdEEhJT6zE1OyoFk+Cs8JRLJllgas+sFnZyH2o941Eqo9Z5tsLesZdjpzMt68TKEMl4mdqh3cnMyCCf5ROJ3Mb7APSuiSpksHBnHrVbPX6tn+WUEubf79aORa4Z4shhWDiljR+Wf0aoPQOnlM3SGZ2j9of9t/H+xudb6If8TR5pE9a2H59y2Pet+E0mCGedmWbUfjVf/cLSFLdWO5tohAEvv8enYD+uL+xw== ARC-Authentication-Results: i=1; lists.ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass (client-ip=211.20.114.72; helo=twmbx01.aspeed.com; envelope-from=jacky_chou@aspeedtech.com; receiver=lists.ozlabs.org) smtp.mailfrom=aspeedtech.com Authentication-Results: lists.ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=aspeedtech.com (client-ip=211.20.114.72; helo=twmbx01.aspeed.com; envelope-from=jacky_chou@aspeedtech.com; receiver=lists.ozlabs.org) Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4bJPzh4HtWz2xKN for ; Fri, 13 Jun 2025 13:30:24 +1000 (AEST) Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 13 Jun 2025 11:30:02 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Fri, 13 Jun 2025 11:30:02 +0800 From: Jacky Chou To: , , , , , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH 4/7] ARM: dts: aspeed-g6: Add AST2600 PCIe RC PERST ctrl pin Date: Fri, 13 Jun 2025 11:29:58 +0800 Message-ID: <20250613033001.3153637-5-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250613033001.3153637-1-jacky_chou@aspeedtech.com> References: <20250613033001.3153637-1-jacky_chou@aspeedtech.com> X-Mailing-List: linux-aspeed@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Add pinctrl support for PCIe RC PERST pin. Signed-off-by: Jacky Chou --- arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi index 289668f051eb..a93e15c64a4b 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi @@ -2,6 +2,11 @@ // Copyright 2019 IBM Corp. &pinctrl { + pinctrl_pcierc1_default: pcierc1_default { + function = "PCIERC1"; + groups = "PCIERC1"; + }; + pinctrl_adc0_default: adc0_default { function = "ADC0"; groups = "ADC0"; -- 2.43.0