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Tue, 24 Jun 2025 15:33:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750779199; bh=q6zc5t1ffrY54UuAj9wfKtHgj2vJk8nzvm5t/rgZlJ4=; h=Date:From:To:Cc:Subject:In-Reply-To:From; b=tAdJn0S2KFY7K9z1dPx1SBSRAXjgZzFEpuX9Cz8uE2gOzckJHxm7jz+0gdwzWO+ex CwT0ZhtL3tH9wwwdwjZBylW6D+MQ0M2HcWcRC2oWuS9rz02Rbu4tw8KGNnF3XJ80hQ iNmEoquScWaakp/njFSojt3F09lCIqgde2eukZOpgCGkqxK8JMJ4CbFm4/h2AGuVwS ITwBL8mhY6G4yj+CNxqP8lp9R651VyBgDXFGPM+uwbPELKLg4tpfsbFb2UGECQ8kOP v4pAFDhjBxAWCSbz34wWUDKlhtjtMzRHLkBhFjVhGsk0f9wG0bP/QpPAl++srzrNwW oQSp5ec0EoFFA== Date: Tue, 24 Jun 2025 10:33:18 -0500 From: Bjorn Helgaas To: Jacky Chou Cc: "bhelgaas@google.com" , "lpieralisi@kernel.org" , "kwilczynski@kernel.org" , "mani@kernel.org" , "robh@kernel.org" , "krzk+dt@kernel.org" , "conor+dt@kernel.org" , "joel@jms.id.au" , "andrew@codeconstruct.com.au" , "vkoul@kernel.org" , "kishon@kernel.org" , "linus.walleij@linaro.org" , "p.zabel@pengutronix.de" , "linux-aspeed@lists.ozlabs.org" , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-phy@lists.infradead.org" , "openbmc@lists.ozlabs.org" , "linux-gpio@vger.kernel.org" , "elbadrym@google.com" , "romlem@google.com" , "anhphan@google.com" , "wak@google.com" , "yuxiaozhang@google.com" , BMC-SW Subject: Re: =?utf-8?B?5Zue6KaGOiBbUEFUQw==?= =?utf-8?Q?H?= 7/7] pci: aspeed: Add ASPEED PCIe host controller driver Message-ID: <20250624153318.GA1477975@bhelgaas> X-Mailing-List: linux-aspeed@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Fri, Jun 20, 2025 at 06:05:20AM +0000, Jacky Chou wrote: > > > Introduce PCIe Root Complex driver for ASPEED SoCs. Support RC > > > initialization, reset, clock, IRQ domain, and MSI domain setup. > > > Implement platform-specific setup and register configuration for > > > ASPEED. And provide PCI config space read/write and INTx/MSI interrupt > > > handling. > > > +static int aspeed_ast2600_rd_conf(struct pci_bus *bus, unsigned int devfn, > > > + int where, int size, u32 *val) > > > +{ > > > + struct aspeed_pcie *pcie = bus->sysdata; > > > + u32 bdf_offset; > > > + int rx_done_fail = 0, slot = PCI_SLOT(devfn); > > > + u32 cfg_val, isr, type = 0; > > > + u32 link_sts = 0; > > > + int ret; > > > + > > > + /* Driver may set unlock RX buffere before triggering next TX config > > > +*/ > > > + writel(PCIE_UNLOCK_RX_BUFF | readl(pcie->reg + H2X_DEV_CTRL), > > > + pcie->reg + H2X_DEV_CTRL); > > > + > > > + if (bus->number == 128 && slot != 0 && slot != 8) > > > + return PCIBIOS_DEVICE_NOT_FOUND; > > > + type = (bus->number > 128); > > > > Weird. What's all this? Some kind of device you want to hide? > > Deserves a hint about what's special. > > The bus range in our AST2600 design is just starting from 128. > There is no something special. I will use the child_ops that is in > struct pci_host_bridge to distinguish the rc bridge and the other > bus. Is the 128 root bus number hardwired into the RC? Maybe it should be described in DT?