From: Bjorn Helgaas <helgaas@kernel.org>
To: Jacky Chou <jacky_chou@aspeedtech.com>
Cc: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
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BMC-SW <BMC-SW@aspeedtech.com>
Subject: Re: [PATCH 7/7] pci: aspeed: Add ASPEED PCIe host controller driver
Date: Tue, 24 Jun 2025 10:40:58 -0500 [thread overview]
Message-ID: <20250624154058.GA1478094@bhelgaas> (raw)
In-Reply-To: <SEYPR06MB5134973F678EB5B163DD50809D79A@SEYPR06MB5134.apcprd06.prod.outlook.com>
On Mon, Jun 23, 2025 at 05:41:13AM +0000, Jacky Chou wrote:
[Apparently you trimmed out some of the lines that show who said what;
there should be more lines here like:
> On Fri, Jun 13, 2025 at 03:03:55PM +0300, Ilpo Järvinen wrote:
> > On Fri, 13 Jun 2025, Jacky Chou wrote:
]
> > > +#include <linux/irqchip/chained_irq.h> #include <linux/irqdomain.h>
> > > +/* TLP configuration type 0 and type 1 */
> > > +#define CRG_READ_FMTTYPE(type) (0x04000000 | (type << 24))
> > > +#define CRG_WRITE_FMTTYPE(type) (0x44000000 | (type << 24))
> >
> > These are straight from PCIe spec, right?
> >
> > I think those should come from defines inside
> > include/uapi/linux/pci_regs.h, there might not be one already, so
> > you might have to add them.
> >
> > I also think you should actually use the type as boolean, and
> > return one of the two defines based on it. A helper to do that
> > might be generic PCI header material as well.
> >
>
> Agreed. This definition is used on TLP header. Maybe I will try to
> add some definitions to pci_regs.h or pci.h
This values might come from the PCIe spec, but unless they are needed
outside drivers/pci, any #defines should probably go in
drivers/pci/pci.h.
next prev parent reply other threads:[~2025-06-24 15:41 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-13 3:29 [PATCH 0/7] Add ASPEED PCIe Root Complex support Jacky Chou
2025-06-13 3:29 ` [PATCH 1/7] dt-bindings: phy: Add document for ASPEED PCIe PHY Jacky Chou
2025-06-13 9:14 ` neil.armstrong
2025-06-20 5:03 ` 回覆: " Jacky Chou
2025-06-13 9:44 ` Krzysztof Kozlowski
2025-06-20 8:29 ` 回覆: " Jacky Chou
2025-06-13 3:29 ` [PATCH 2/7] dt-bindings: pci: Add document for ASPEED PCIe Config Jacky Chou
2025-06-13 9:46 ` Krzysztof Kozlowski
2025-06-20 8:32 ` 回覆: " Jacky Chou
2025-06-13 15:58 ` Bjorn Helgaas
2025-06-20 5:27 ` Jacky Chou
2025-06-13 3:29 ` [PATCH 3/7] dt-bindings: pci: Add document for ASPEED PCIe RC Jacky Chou
2025-06-13 9:50 ` Krzysztof Kozlowski
2025-06-20 8:36 ` Jacky Chou
2025-06-25 21:04 ` Rob Herring
2025-06-27 9:59 ` 回覆: " Jacky Chou
2025-06-13 3:29 ` [PATCH 4/7] ARM: dts: aspeed-g6: Add AST2600 PCIe RC PERST ctrl pin Jacky Chou
2025-06-13 9:51 ` Krzysztof Kozlowski
2025-06-20 8:36 ` Jacky Chou
2025-06-13 15:59 ` Bjorn Helgaas
2025-06-13 3:29 ` [PATCH 5/7] ARM: dts: aspeed-g6: Add PCIe RC node Jacky Chou
2025-06-13 15:54 ` Bjorn Helgaas
2025-06-20 5:24 ` 回覆: " Jacky Chou
2025-06-24 15:28 ` Bjorn Helgaas
2025-06-25 8:27 ` 回覆: " Jacky Chou
2025-06-25 22:16 ` Bjorn Helgaas
2025-06-27 10:02 ` Jacky Chou
2025-06-13 3:30 ` [PATCH 6/7] pinctrl: aspeed-g6: Add PCIe RC PERST pin group Jacky Chou
2025-06-18 12:15 ` Linus Walleij
2025-06-20 7:09 ` Andrew Jeffery
2025-06-13 3:30 ` [PATCH 7/7] pci: aspeed: Add ASPEED PCIe host controller driver Jacky Chou
2025-06-13 9:54 ` Krzysztof Kozlowski
2025-06-23 2:42 ` 回覆: " Jacky Chou
2025-06-13 12:03 ` Ilpo Järvinen
2025-06-23 5:41 ` Jacky Chou
2025-06-24 10:50 ` Ilpo Järvinen
2025-06-24 11:11 ` 回覆: " Jacky Chou
2025-06-24 15:40 ` Bjorn Helgaas [this message]
2025-06-25 8:32 ` Jacky Chou
2025-06-13 16:28 ` Bjorn Helgaas
2025-06-20 6:05 ` 回覆: " Jacky Chou
2025-06-24 15:33 ` Bjorn Helgaas
2025-06-14 2:07 ` kernel test robot
2025-06-19 8:14 ` kernel test robot
2025-06-13 9:18 ` [PATCH 0/7] Add ASPEED PCIe Root Complex support neil.armstrong
2025-06-20 8:20 ` 回覆: " Jacky Chou
2025-06-24 7:29 ` Neil Armstrong
2025-06-24 10:54 ` 回覆: " Jacky Chou
2025-06-16 21:46 ` Rob Herring (Arm)
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