From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BBE2DC83F1B for ; Sat, 12 Jul 2025 02:50:11 +0000 (UTC) Received: from boromir.ozlabs.org (localhost [127.0.0.1]) by lists.ozlabs.org (Postfix) with ESMTP id 4bfCjt3HhXz2yRD; Sat, 12 Jul 2025 12:50:10 +1000 (AEST) Authentication-Results: lists.ozlabs.org; arc=none smtp.remote-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=lists.ozlabs.org; s=201707; t=1752044914; cv=none; b=G7bdRnKuznavsZz5vUL2r1bEBQoUHKmy7DDpY58voRTuoo5SpRwY6g8tWgtAZE6IH61KC58zDLQQQTu+nQ3KzE5GN5e33cg5Qj9oWzAdzjcr/k40/MFDx9wv7Zz89zrfftPr7ofG9XdwxBIONKrBlG1YqdceLj7N6g0zzwlHTdltRlz94pcyrg8oeL5TBuRyDgwm+e7KeKLGm5lkmjQAeUDdF0qzt/ybEH5K9AXYJEN6Du7LLytVSKcsD5Vn/vTvQ+ntC+QYeZYNOE9hG8S2cgaCKkCoHPsVgh5fjG3b3mn8JeUsGxZk64qtzemL4Y8/UkExmf4S/lGkG1RKySGOcw== ARC-Message-Signature: i=1; a=rsa-sha256; d=lists.ozlabs.org; s=201707; t=1752044914; c=relaxed/relaxed; bh=5AR4gXAZXb+yXxeBaXxlmxm5zufcseHNq6stVGKiC2Y=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=J17Sq0bFTdXcgLrE4wFqTR2KzEpKz1NAeV0E3XtkrVYUm3GrudCL6AO0hDGXxtxUe/UlIoGfAOsXL+XQmQ/7OWzI2n1RubbR/iUjpuN7hby9yqhEnKGQNgUX5nJf/PSUU7Z469lpQeOfRUGbNhr0c6fDqNs3SreynvE8e7LMK4aHlFc7hZ+FzwZCYJEbLTzO2oD/JbPSJh/w33OrlD835kPrYBp5i1qoQAe3FZW47wzlLrdBhqwUnSgWXu3aSmAWsTuo5BYxe2legDiculu5LfAXbP/EhE0ShuDBT14LqMuj+mD2Wjv7y5V11QmE3XHMo+N1Pi7TDoSN/cCNWgYJtw== ARC-Authentication-Results: i=1; lists.ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass (client-ip=211.20.114.72; helo=twmbx01.aspeed.com; envelope-from=jacky_chou@aspeedtech.com; receiver=lists.ozlabs.org) smtp.mailfrom=aspeedtech.com Authentication-Results: lists.ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=aspeedtech.com (client-ip=211.20.114.72; helo=twmbx01.aspeed.com; envelope-from=jacky_chou@aspeedtech.com; receiver=lists.ozlabs.org) Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4bcTbP5rZqz2xQ5 for ; Wed, 9 Jul 2025 17:08:33 +1000 (AEST) Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 9 Jul 2025 15:08:09 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 9 Jul 2025 15:08:09 +0800 From: Jacky Chou To: , , , , , , , , , , , , , , , , , , , , , , CC: , Conor Dooley Subject: [net-next v4 2/4] dt-bindings: clock: ast2600: Add reset definitions for MAC1 and MAC2 Date: Wed, 9 Jul 2025 15:08:07 +0800 Message-ID: <20250709070809.2560688-3-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250709070809.2560688-1-jacky_chou@aspeedtech.com> References: <20250709070809.2560688-1-jacky_chou@aspeedtech.com> X-Mailing-List: linux-aspeed@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Add ASPEED_RESET_MAC1 and ASPEED_RESET_MAC2 reset definitions to the ast2600-clock binding header. These are required for proper reset control of the MAC1 and MAC2 ethernet controllers on the AST2600 SoC. Signed-off-by: Jacky Chou Acked-by: Conor Dooley Acked-by: Stephen Boyd --- include/dt-bindings/clock/ast2600-clock.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h index 7ae96c7bd72f..f60fff261130 100644 --- a/include/dt-bindings/clock/ast2600-clock.h +++ b/include/dt-bindings/clock/ast2600-clock.h @@ -122,6 +122,8 @@ #define ASPEED_RESET_PCIE_DEV_OEN 20 #define ASPEED_RESET_PCIE_RC_O 19 #define ASPEED_RESET_PCIE_RC_OEN 18 +#define ASPEED_RESET_MAC2 12 +#define ASPEED_RESET_MAC1 11 #define ASPEED_RESET_PCI_DP 5 #define ASPEED_RESET_HACE 4 #define ASPEED_RESET_AHB 1 -- 2.34.1