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Fri, 22 Aug 2025 15:36:14 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C9AE6C4CEED; Fri, 22 Aug 2025 15:36:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755876974; bh=M4axMQs8H13c09qWo6K3CitPMFiulFvZkPJOaBof5qk=; h=Date:From:To:Cc:Subject:In-Reply-To:From; b=Gkm3JskIl9AEISSDTxGOPEQ5Ekw+yO/AvQdomznGVF8QhL2AKSjB9ug0fr1l8cDAC R5sn0gLRNWsiAEXDV/8IqKrKhmFhfaIV0eZ2Ifeh4tLF63tK6IWjZnREefRXi/M03D sonYkEFxAHk5WnTO9vZYeGm/kLZ++fqGgDYfTihFHvZFAojKUxRz39rTZqvajG+zmS C5cdC9xRurIk0OtWquWGUHHvSsQMbdCi9wn8LX+sUhjGWTlzoGERhtdVdDoJXui0e5 RMD+nlwye1ZCE/pFkHY1ti7fjopPKBrl36OGkQOSbkQ95P59TCZ58RYnkJ70Qa5E+H M8+0Xh8w08Hdg== Date: Fri, 22 Aug 2025 10:36:11 -0500 From: Bjorn Helgaas To: Jacky Chou Cc: "bhelgaas@google.com" , "lpieralisi@kernel.org" , "kwilczynski@kernel.org" , "mani@kernel.org" , "robh@kernel.org" , "krzk+dt@kernel.org" , "conor+dt@kernel.org" , "joel@jms.id.au" , "andrew@codeconstruct.com.au" , "linux-aspeed@lists.ozlabs.org" , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "openbmc@lists.ozlabs.org" , "linux-gpio@vger.kernel.org" , "linus.walleij@linaro.org" , "p.zabel@pengutronix.de" , BMC-SW Subject: Re: =?utf-8?B?5Zue6KaG?= =?utf-8?Q?=3A?= [PATCH v2 09/10] PCI: aspeed: Add ASPEED PCIe RC driver Message-ID: <20250822153611.GA684739@bhelgaas> X-Mailing-List: linux-aspeed@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Fri, Aug 22, 2025 at 07:00:25AM +0000, Jacky Chou wrote: > > v1 posting was > > https://lore.kernel.org/r/20250613033001.3153637-1-jacky_chou@aspeedtech > > .com > > Links to previous postings are helpful in the cover letter. > > > > On Tue, Jul 15, 2025 at 11:43:19AM +0800, Jacky Chou wrote: > > > Introduce PCIe Root Complex driver for ASPEED SoCs. Support RC > > > initialization, reset, clock, IRQ domain, and MSI domain setup. > > > Implement platform-specific setup and register configuration for > > > ASPEED. And provide PCI config space read/write and INTx/MSI interrupt > > > handling. > > > +#define MAX_MSI_HOST_IRQS 64 > > > +#define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 500 > > > > Where does this value come from? Is there a generic value from > > drivers/pci/pci.h you can use? > > We check the PCIe specification to find these contents. > > "With a Downstream Port that supports Link speeds greater than 5.0 > GT/s, software must wait a minimum of 100 ms after Link training > completes before sending a Configuration Request to the device > immediately below that Port." > > So, we think delay 500ms to let kernel issue the first configuration > command is enough after deassert PERST. Isn't this PCIE_RESET_CONFIG_WAIT_MS? I prefer to use #defines from the PCI core whenever possible because it makes it easier to ensure that all drivers include the required delays. > > > +#define PCIE_RESET_CONFIG_RC_WAIT_MS 10 > > > > Ditto. If it's an Aspeed-specific value, can you point to the > > source in the Aspeed datasheet? > > This delay is set to ensure that the RC internal settings are > completely reset. We do not put its usage in our datasheet. The "PCIE_" prefix suggests something required by the PCIe base spec. If this is an Aspeed-specific value, perhaps remove the "PCIE_" prefix? > > > +static int aspeed_ast2700_child_config(struct pci_bus *bus, unsigned int > > devfn, > > > + int where, int size, u32 *val, > > > + bool write) > > > +{ > > > + struct aspeed_pcie *pcie = bus->sysdata; > > > + u32 bdf_offset, status, cfg_val; > > > + int ret; > > > + > > > + bdf_offset = aspeed_pcie_get_bdf_offset(bus, devfn, where); > > > + > > > + cfg_val = CRG_PAYLOAD_SIZE; > > > + if (write) > > > + cfg_val |= (bus->number == 1) ? CRG0_WRITE_FMTTYPE : > > CRG1_WRITE_FMTTYPE; > > > + else > > > + cfg_val |= (bus->number == 1) ? CRG0_READ_FMTTYPE : > > > +CRG1_READ_FMTTYPE; > > > > I don't think you should assume that bus 0 is the root bus. The root bus > > number should come from the DT bus-range. Just making sure you saw this part since you didn't mention it. Bjorn