From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0B3ABCCF9E0 for ; Mon, 27 Oct 2025 09:59:58 +0000 (UTC) Received: from boromir.ozlabs.org (localhost [127.0.0.1]) by lists.ozlabs.org (Postfix) with ESMTP id 4cw8920K5lz3c8W; Mon, 27 Oct 2025 20:58:46 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; arc=none smtp.remote-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=lists.ozlabs.org; s=201707; t=1761559126; cv=none; b=f2/Qu726LXCME0Gyq1i/DH0YL2qn9q5LTIDPBGkAmi1XpqaHlxaEYd/p0DPQMLycbT8Sx5rdESHCKksWzNVk3scaJ/fCMzxG48XGg2xrkQF+Wkq+6DcrBixPfrZ3toLkAFJ8TPuGqiTbSFrEqdyoLCUSwCotIdym1xQ7Z1NSPoumCP0rUzIEIms6rY+PiU9If+xuIz9414EKBypGcN161FZ6TKp2TFo2dfYvXG4QK29D+iVG1pox2gDlwTgN1hJIx3xsyIpVeHvPxGI4f0g3ilDTzlqEObiOy+vu853+GX7CwZ/o2K+HzCXFSv1BtkzI0FQcOnz08SOiqmGPAtzMNQ== ARC-Message-Signature: i=1; a=rsa-sha256; d=lists.ozlabs.org; s=201707; t=1761559126; c=relaxed/relaxed; bh=O7yNhNuvc8VG3yl08jHfoKN/yF/kNl8k3Xx/b4i4wNQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Vjs1sQEW8iXAJE+skDW2skjvwPUtSVfhIePAP9nZLj/8bDVrYl0oFduFV1Y96a8meEaY5hSS4doj5CnGM8UKIyt0+x+oH9GdOCFS2KrWMk+pAVCBCma8I8Jkv9szvfUbz2yXqz7bVag25A5kmquO1sIDyAOTxtMReqnzuOeFl3oaHSzXMe5w/oxqYaumEUD5LmOaA8NMTHco7L1HQGX+X7LwZZ3bYNOUNU2vm3y66hfLc3eqxGS+aFyPL4q0SkNfuCh6wn7HMVOSiGa2YuOhd8RRAozwRFj6ccN0wulsz2w5jMezAg0dGju84os+S79cqetjyrlXQ5RMnpYbz/VJyg== ARC-Authentication-Results: i=1; lists.ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass (client-ip=211.20.114.72; helo=twmbx01.aspeed.com; envelope-from=jacky_chou@aspeedtech.com; receiver=lists.ozlabs.org) smtp.mailfrom=aspeedtech.com Authentication-Results: lists.ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=aspeedtech.com (client-ip=211.20.114.72; helo=twmbx01.aspeed.com; envelope-from=jacky_chou@aspeedtech.com; receiver=lists.ozlabs.org) Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4cw8913zk9z3cZW; Mon, 27 Oct 2025 20:58:45 +1100 (AEDT) Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 27 Oct 2025 17:58:26 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 27 Oct 2025 17:58:26 +0800 From: Jacky Chou To: , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v4 5/9] ARM: dts: aspeed-g6: Add PCIe RC and PCIe PHY node Date: Mon, 27 Oct 2025 17:58:21 +0800 Message-ID: <20251027095825.181161-6-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251027095825.181161-1-jacky_chou@aspeedtech.com> References: <20251027095825.181161-1-jacky_chou@aspeedtech.com> X-Mailing-List: linux-aspeed@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain The AST2600 has one PCIe RC and add the PCIe PHY for RC. Signed-off-by: Jacky Chou --- arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 54 +++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi index f8662c8ac089..916e68fedc5a 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -379,6 +379,60 @@ rng: hwrng@1e6e2524 { quality = <100>; }; + pcie_phy1: phy@1e6ed200 { + compatible = "aspeed,ast2600-pcie-phy"; + reg = <0x1e6ed200 0x100>; + #phy-cells = <0>; + }; + + pcie0: pcie@1e770000 { + compatible = "aspeed,ast2600-pcie"; + device_type = "pci"; + reg = <0x1e770000 0x100>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = ; + bus-range = <0x00 0xff>; + + ranges = <0x01000000 0x0 0x00018000 0x00018000 0x0 0x00008000 + 0x02000000 0x0 0x60000000 0x60000000 0x0 0x20000000>; + + status = "disabled"; + + resets = <&syscon ASPEED_RESET_H2X>; + reset-names = "h2x"; + pinctrl-0 = <&pinctrl_pcierc1_default>; + pinctrl-names = "default"; + + #interrupt-cells = <1>; + msi-controller; + + aspeed,ahbc = <&ahbc>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + + pcie@8,0 { + reg = <0x804000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + resets = <&syscon ASPEED_RESET_PCIE_RC_O>; + reset-names = "perst"; + clocks = <&syscon ASPEED_CLK_GATE_BCLK>; + phys = <&pcie_phy1>; + ranges; + }; + }; + gfx: display@1e6e6000 { compatible = "aspeed,ast2600-gfx", "syscon"; reg = <0x1e6e6000 0x1000>; -- 2.34.1