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From: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
To: <robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
	<joel@jms.id.au>, <andrew@codeconstruct.com.au>, <clg@kaod.org>,
	<clg@redhat.com>, <broonie@kernel.org>,
	<devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-aspeed@lists.ozlabs.org>, <linux-kernel@vger.kernel.org>,
	<openbmc@lists.ozlabs.org>, <linux-spi@vger.kernel.org>,
	<BMC-SW@aspeedtech.com>
Subject: [PATCH v2 2/4] spi: aspeed: Enable Quad SPI mode for page program
Date: Fri, 14 Nov 2025 18:10:40 +0800	[thread overview]
Message-ID: <20251114101042.1520997-3-chin-ting_kuo@aspeedtech.com> (raw)
In-Reply-To: <20251114101042.1520997-1-chin-ting_kuo@aspeedtech.com>

Ensure the controller switches to quad I/O mode when
spi-tx-bus-width dts property is 4 and the Quad SPI program
opcode (32h or 34h) is used. Without this change, high-bit
data will be lost during page programming.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
---
 drivers/spi/spi-aspeed-smc.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
index 179c47ffbfeb..4163632fed8b 100644
--- a/drivers/spi/spi-aspeed-smc.c
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -263,11 +263,15 @@ static ssize_t aspeed_spi_write_user(struct aspeed_spi_chip *chip,
 				     const struct spi_mem_op *op)
 {
 	int ret;
+	int io_mode = aspeed_spi_get_io_mode(op);
 
 	aspeed_spi_start_user(chip);
 	ret = aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, op->addr.val, op->cmd.opcode);
 	if (ret < 0)
 		goto stop_user;
+
+	aspeed_spi_set_io_mode(chip, io_mode);
+
 	aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out, op->data.nbytes);
 stop_user:
 	aspeed_spi_stop_user(chip);
-- 
2.34.1



  parent reply	other threads:[~2025-11-14 10:11 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-14 10:10 [PATCH v2 0/4] spi: aspeed: Add AST2700 SoC support and Quad SPI handling update Chin-Ting Kuo
2025-11-14 10:10 ` [PATCH v2 1/4] dt-bindings: spi: aspeed,ast2600-fmc: Add AST2700 SoC support Chin-Ting Kuo
2025-11-14 10:10 ` Chin-Ting Kuo [this message]
2025-11-14 10:10 ` [PATCH v2 3/4] spi: aspeed: Use phys_addr_t for bus addresses to support 64-bit platforms Chin-Ting Kuo
2025-11-14 10:10 ` [PATCH v2 4/4] spi: aspeed: Add support for the AST2700 SPI controller Chin-Ting Kuo
2025-11-20  9:40 ` [PATCH v2 0/4] spi: aspeed: Add AST2700 SoC support and Quad SPI handling update Mark Brown

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