From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 502A5CEBF96 for ; Mon, 17 Nov 2025 12:39:27 +0000 (UTC) Received: from boromir.ozlabs.org (localhost [127.0.0.1]) by lists.ozlabs.org (Postfix) with ESMTP id 4d96kQ22w5z30Cd; Mon, 17 Nov 2025 23:39:10 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; arc=none smtp.remote-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=lists.ozlabs.org; s=201707; t=1763383150; cv=none; b=e8UQqJoa0LEDDKSIx1Szmyo3EUIgytlMsHco2g+NxTiV0jzrCVYXQixK6Tn/GW4u1Sc/iVFssQY0WwWIebs6VYVXJday2j2f28tTr4048D7wZop/DQHrxnNsmE3RufNwN48Koi2p+JctVDuoQkFFmNNugbrdWNaTjWPrd61KcF11kvfsGRscJxSVnSFydK1A75GmCJffGvNi94YEZjGZh9Q+Xbd1LZtR9s6BVCkgIAN5tA546/BXy9MRAIoKt1/2ixQFIt9m2edpTXwNl4UcCfzRVgwrSVUDlUXUbc227s4KQq9YKh4T/r0S59X29oK8sFS2yNexIWxodiVy9VZZfg== ARC-Message-Signature: i=1; a=rsa-sha256; d=lists.ozlabs.org; s=201707; t=1763383150; c=relaxed/relaxed; bh=LVMAtFSJkOmWLNQOjwD3PHOyrL1IbxHoq2jDW6dhuac=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=JI9EMm5m64kKUR51KeGRFldL98Nu6Gds/2K7onA6wRc9k2poxBdjSOQItsqFQ+TrrwDIR7lFRX5Tr8daJrjkn/Roqww9LqgPJBHl3Ll/p5P3CQdh1s8aS8SPur1eVW7SUGBV6UNXLrdgUS2wNKIzxRhfZf8N8vfAK1YkwnXnx6snHyzJefXohQeDg4UwsIaMB3wjJdHWi2eda8u5l7DbvWTIiXjh9jfowJ0xmCrKgzolpQwlaqCu/H5mvL8SHZXyXa73vgOK8HVn4qzqC7pfoUJdqm26vZBYqlexEoCtgCGODC2vpdiPZMB5SnVhlKAkjMAsV1Bx83DUhUHYzJ72aw== ARC-Authentication-Results: i=1; lists.ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass (client-ip=211.20.114.72; helo=twmbx01.aspeed.com; envelope-from=jacky_chou@aspeedtech.com; receiver=lists.ozlabs.org) smtp.mailfrom=aspeedtech.com Authentication-Results: lists.ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=aspeedtech.com (client-ip=211.20.114.72; helo=twmbx01.aspeed.com; envelope-from=jacky_chou@aspeedtech.com; receiver=lists.ozlabs.org) Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4d96kP3CKlz2yx7; Mon, 17 Nov 2025 23:39:09 +1100 (AEDT) Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 17 Nov 2025 20:38:52 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 17 Nov 2025 20:38:52 +0800 From: Jacky Chou Date: Mon, 17 Nov 2025 20:37:48 +0800 Subject: [PATCH v5 1/8] dt-bindings: phy: aspeed: Add ASPEED PCIe PHY X-Mailing-List: linux-aspeed@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20251117-upstream_pcie_rc-v5-1-b4a198576acf@aspeedtech.com> References: <20251117-upstream_pcie_rc-v5-0-b4a198576acf@aspeedtech.com> In-Reply-To: <20251117-upstream_pcie_rc-v5-0-b4a198576acf@aspeedtech.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , "Andrew Jeffery" , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , "Manivannan Sadhasivam" , Linus Walleij , Philipp Zabel CC: , , , , , , Andrew Jeffery , , , Jacky Chou X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1763383131; l=1554; i=jacky_chou@aspeedtech.com; s=20251031; h=from:subject:message-id; bh=nSo81XDH3g+0IhsQkmlg4apJPpZay88RgQZ5h1VpL2k=; b=EOc7vQFreOGxcFvq4SKAkure6YgomxEmno4xPRCbpV9yD0s9jwevXR80DRoLqmNOI22YR4aFE E7FHqToB/cwBypT8YGK7y58NtslpyZ9A6khmzX28ng2Udch61I/vzCR X-Developer-Key: i=jacky_chou@aspeedtech.com; a=ed25519; pk=8XBx7KFM1drEsfCXTH9QC2lbMlGU4XwJTA6Jt9Mabdo= Introduce device-binding for ASPEED AST2600/2700 PCIe PHY. The PCIe PHY is used for PCIe RC to configure as RC mode. Signed-off-by: Jacky Chou Reviewed-by: Rob Herring (Arm) --- .../bindings/phy/aspeed,ast2600-pcie-phy.yaml | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml new file mode 100644 index 000000000000..71a5cd91fb3f --- /dev/null +++ b/Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/aspeed,ast2600-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED PCIe PHY + +maintainers: + - Jacky Chou + +description: + The ASPEED PCIe PHY provides the physical layer functionality for PCIe + controllers in the SoC. + +properties: + compatible: + items: + - enum: + - aspeed,ast2600-pcie-phy + - aspeed,ast2700-pcie-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@1e6ed200 { + compatible = "aspeed,ast2600-pcie-phy"; + reg = <0x1e6ed200 0x100>; + #phy-cells = <0>; + }; -- 2.34.1