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Thu, 4 Dec 2025 19:53:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1764878038; bh=IlWhPGE3xUkVs9noGqN8k3YfY0Ubf/0Tz/7YbiNoNOw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=CRDyqcy+7t1NqBpjwfvt6EVa8fBQkxIXQGm3UhSM6pF/wQO2GB/GsLsPVU/5x5GEi ISuzg0kUbHZykMWfUetqINwESVLOMc5Fmkby09hgB/u7SERCzYnp0wawyGV2PlT7/n 5l87bi2MeH9BDcFb4RYVZv5QJbaJ1y96IceT5JXqsVQb4D3G9VqtQmvZmKYyR8TlJc Kvw7JWiTUYPVYuFB9UIihbWz7Pzyesd0xuz9ohN9oj0Fd4ZSSgOfGwZqBkdh2dU7D4 SjUBhWCsYAnJLC6nKdnqRUem9TAlPRZT3hfEV3yMJUy6kE89pMlaWtQcaBAKjIyVu9 WVBxr11PatfhA== Date: Thu, 4 Dec 2025 13:53:55 -0600 From: Rob Herring To: Jacky Chou Cc: Vinod Koul , Kishon Vijay Abraham I , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Bjorn Helgaas , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Linus Walleij , Philipp Zabel , linux-aspeed@lists.ozlabs.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andrew Jeffery , openbmc@lists.ozlabs.org, linux-gpio@vger.kernel.org Subject: Re: [PATCH v6 0/7] Add ASPEED PCIe Root Complex support Message-ID: <20251204195355.GA1975043-robh@kernel.org> References: <20251201-upstream_pcie_rc-v6-0-8c8800c56b16@aspeedtech.com> X-Mailing-List: linux-aspeed@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251201-upstream_pcie_rc-v6-0-8c8800c56b16@aspeedtech.com> On Mon, Dec 01, 2025 at 02:29:10PM +0800, Jacky Chou wrote: > This patch series adds support for the ASPEED PCIe Root Complex, > including device tree bindings, pinctrl support, and the PCIe host controller > driver. The patches introduce the necessary device tree nodes, pinmux groups, > and driver implementation to enable PCIe functionality on ASPEED platforms. > Currently, the ASPEED PCIe Root Complex only supports a single port. > > Summary of changes: > - Add device tree binding documents for ASPEED PCIe PHY, PCIe Config, and PCIe RC > - Update MAINTAINERS for new bindings and driver > - Add PCIe RC node and PERST control pin to aspeed-g6 device tree > - Implement ASPEED PCIe PHY driver > - Implement ASPEED PCIe Root Complex host controller driver > > This series has been tested on AST2600/AST2700 platforms and enables PCIe device > enumeration and operation. > > Signed-off-by: Jacky Chou > --- > Changes in v6: > - Refer to pci-cpi-bridge.yaml to update aspeed,ast2600-pcie.yaml and > the pcie node of aspeed-g6.dtsi. Where is this? You don't describe the root port and its properties at all now. > - 'dt-bindings: pinctrl: aspeed,ast2600-pinctrl: Add PCIe RC PERST# > group' have applied, remove it from this version. > - Adjust the defnitions in pci.h. > - Link to v5: https://lore.kernel.org/r/20251117-upstream_pcie_rc-v5-0-b4a198576acf@aspeedtech.com