From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 64C08105F786 for ; Fri, 13 Mar 2026 10:02:43 +0000 (UTC) Received: from boromir.ozlabs.org (localhost [127.0.0.1]) by lists.ozlabs.org (Postfix) with ESMTP id 4fXKmK5x1Lz3cJk; Fri, 13 Mar 2026 21:02:41 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; arc=none smtp.remote-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=lists.ozlabs.org; s=201707; t=1773396161; cv=none; b=Px/tvjPTHfTb2ilsQyxhhHKTDAgjV0U8TFrEbNkntTH94sDRddHZFREPSlVmEaflBfr0yiFruZtxXuSz5Zgjgn6KqXkcMj5X7rB7+8A2EnCUzUq3HOj0BhPGt/osVJclqQIsDmOBkygsGHghmdtYEPP7K1lqED54lWcAwSHuLklUtv2TD+DAmJ8/c/O3u+LRiD2MSQua4/FI2yhFNqMt0v7Ba6OdwIKC79jGNjP3PQS1HQE5v3izwidcts2bVUNBZ4BEvhdDqR+evGo8MHenN/4W8l/fsA9vlLlmOtYFnLZikACVxT+D/bHO6wk6qiIwL/XpoM9Xb76isgW/dyylHw== ARC-Message-Signature: i=1; a=rsa-sha256; d=lists.ozlabs.org; s=201707; t=1773396161; c=relaxed/relaxed; bh=A939J4iWGdtlVWArFdZqUZziIm4200CdJ3vSkDQy8t4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:To:CC; b=U0E2BO1YyvqfO52B6gVOW5+LfSGXIg0IPUCHQ05KYBn/wfGt8XQjpmMlSgOU4WDGhSp8+6PWettqK2c6/NRjEv5tVvrhQ3TqXIGSRwXaARa41hvfe5ESDjyPR2ErPKtInxQiCATkT0HQOBbiwQWhda1/S594IVR+VuN/3f8NnViAp2g+cimQa2WwqSJ8QGQYj1inlNaBPoYUSpoOZKn+QSGHRkhG34AoUFVBPv6ASm/ohS7GaG3qP0ssHKSjtwI9/UsLqoGmvyEzkiHkiIRV4p5BQh0tR7cA0hwt9fwnCu1F5f5XB3zOCAxUNcaaV3xRRPceq4gBIxdlGOfn1Ztgtw== ARC-Authentication-Results: i=1; lists.ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass (client-ip=211.20.114.72; helo=twmbx01.aspeed.com; envelope-from=billy_tsai@aspeedtech.com; receiver=lists.ozlabs.org) smtp.mailfrom=aspeedtech.com Authentication-Results: lists.ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=aspeedtech.com (client-ip=211.20.114.72; helo=twmbx01.aspeed.com; envelope-from=billy_tsai@aspeedtech.com; receiver=lists.ozlabs.org) Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4fXKmJ6LQPz3cGf for ; Fri, 13 Mar 2026 21:02:40 +1100 (AEDT) Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 13 Mar 2026 18:02:24 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Fri, 13 Mar 2026 18:02:24 +0800 From: Billy Tsai Date: Fri, 13 Mar 2026 18:02:16 +0800 Subject: [PATCH] iio: adc: aspeed: Reserve battery sensing channel for on-demand use X-Mailing-List: linux-aspeed@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20260313-adc-v1-1-7a2edb4e5664@aspeedtech.com> X-B4-Tracking: v=1; b=H4sIAKfgs2kC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIzMDY0Nj3cSUZF0Tc8skg8QkA8ukxFQloMqCotS0zAqwKdGxtbUA9f8ANlU AAAA= X-Change-ID: 20260313-adc-479b0ab09bae To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , "Andy Shevchenko" , Joel Stanley , Andrew Jeffery CC: , , , , , Billy Tsai X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773396144; l=6286; i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id; bh=EUOMjFM/rFziWkFH4VEIzdpUTOeldEDjn+7qcp7rxEU=; b=Xdi0AH3kN54e+ecLGXWjtxc7b+xDzUWduaZgLFqjkrogFUSi/KvCrfGlJtR0QmP5YdPGmMu0T t6RU8GR6a30DS4/VyYBoJNw5xiFAQstlILViGDMnPRhmy8HU4rJCFwR X-Developer-Key: i=billy_tsai@aspeedtech.com; a=ed25519; pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ= For controllers with battery sensing capability (AST2600/AST2700), the last channel uses a different circuit design optimized for battery voltage measurement. This channel should not be enabled by default along with other channels to avoid potential interference and power efficiency issues. Changes made: - Introduce aspeed_adc_get_active_channels() to return the number of channels that should be enabled by default - For battery sensing capable controllers, exclude the last channel from the default channel enable mask - Enable the battery sensing channel only when explicitly accessed via read_raw() - Replace hardcoded channel numbers with ASPEED_ADC_BATTERY_CHANNEL macro - Add helper functions for cleaner channel management This ensures optimal power efficiency for normal ADC operations while maintaining full functionality when battery sensing is needed. Signed-off-by: Billy Tsai --- drivers/iio/adc/aspeed_adc.c | 88 ++++++++++++++++++++++++++++++++++++++------ 1 file changed, 76 insertions(+), 12 deletions(-) diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c index 4be44c524b4d..376a024341e3 100644 --- a/drivers/iio/adc/aspeed_adc.c +++ b/drivers/iio/adc/aspeed_adc.c @@ -73,6 +73,31 @@ #define ASPEED_ADC_CTRL_CHANNEL GENMASK(31, 16) #define ASPEED_ADC_CTRL_CHANNEL_ENABLE(ch) FIELD_PREP(ASPEED_ADC_CTRL_CHANNEL, BIT(ch)) +/* + * Enable multiple consecutive channels starting from channel 0. + * This creates a bitmask for channels 0 to (num_channels - 1). + * For example: num_channels=3 creates mask 0x0007 (channels 0,1,2) + */ +static inline u32 aspeed_adc_channels_mask(unsigned int num_channels) +{ + if (num_channels == 0) + return 0; + if (num_channels >= 16) + return GENMASK(15, 0); + return GENMASK(num_channels - 1, 0); +} + +/* + * Helper function to enable multiple channels in the control register + */ +static inline u32 aspeed_adc_enable_channels(unsigned int num_channels) +{ + return FIELD_PREP(ASPEED_ADC_CTRL_CHANNEL, aspeed_adc_channels_mask(num_channels)); +} + +/* Battery sensing is typically on the last channel */ +#define ASPEED_ADC_BATTERY_CHANNEL 7 + #define ASPEED_ADC_INIT_POLLING_TIME 500 #define ASPEED_ADC_INIT_TIMEOUT 500000 /* @@ -121,6 +146,18 @@ struct aspeed_adc_data { struct adc_gain battery_mode_gain; }; +static inline unsigned int aspeed_adc_get_active_channels(const struct aspeed_adc_data *data) +{ + /* + * For controllers with battery sensing capability, the last channel + * is reserved for battery sensing and should not be included in + * normal channel operations. + */ + if (data->model_data->bat_sense_sup) + return data->model_data->num_channels - 1; + return data->model_data->num_channels; +} + #define ASPEED_CHAN(_idx, _data_reg_addr) { \ .type = IIO_VOLTAGE, \ .indexed = 1, \ @@ -281,13 +318,35 @@ static int aspeed_adc_read_raw(struct iio_dev *indio_dev, int *val, int *val2, long mask) { struct aspeed_adc_data *data = iio_priv(indio_dev); - u32 adc_engine_control_reg_val; + u32 adc_engine_control_reg_val = readl(data->base + ASPEED_REG_ENGINE_CONTROL); switch (mask) { case IIO_CHAN_INFO_RAW: - if (data->battery_sensing && chan->channel == 7) { - adc_engine_control_reg_val = - readl(data->base + ASPEED_REG_ENGINE_CONTROL); + /* + * For battery sensing capable controllers, we need to enable + * the specific channel before reading. This is required because + * the battery channel may not be enabled by default. + */ + if (data->model_data->bat_sense_sup && + chan->channel == ASPEED_ADC_BATTERY_CHANNEL) { + u32 ctrl_reg = adc_engine_control_reg_val & ~ASPEED_ADC_CTRL_CHANNEL; + + ctrl_reg |= ASPEED_ADC_CTRL_CHANNEL_ENABLE(chan->channel); + writel(ctrl_reg, data->base + ASPEED_REG_ENGINE_CONTROL); + /* + * After enable a new channel need to wait some time for adc stable + * Experiment result is 1ms. + */ + mdelay(1); + } + + /* + * Battery sensing mode requires special configuration: + * - Set channel 7 to battery mode + * - Enable battery sensing functionality + * - Apply voltage divider compensation + */ + if (data->battery_sensing && chan->channel == ASPEED_ADC_BATTERY_CHANNEL) { writel(adc_engine_control_reg_val | FIELD_PREP(ASPEED_ADC_CH7_MODE, ASPEED_ADC_CH7_BAT) | @@ -301,15 +360,15 @@ static int aspeed_adc_read_raw(struct iio_dev *indio_dev, *val = readw(data->base + chan->address); *val = (*val * data->battery_mode_gain.mult) / data->battery_mode_gain.div; - /* Restore control register value */ - writel(adc_engine_control_reg_val, - data->base + ASPEED_REG_ENGINE_CONTROL); } else *val = readw(data->base + chan->address); + /* Restore control register value */ + writel(adc_engine_control_reg_val, + data->base + ASPEED_REG_ENGINE_CONTROL); return IIO_VAL_INT; case IIO_CHAN_INFO_OFFSET: - if (data->battery_sensing && chan->channel == 7) + if (data->battery_sensing && chan->channel == ASPEED_ADC_BATTERY_CHANNEL) *val = (data->cv * data->battery_mode_gain.mult) / data->battery_mode_gain.div; else @@ -607,10 +666,15 @@ static int aspeed_adc_probe(struct platform_device *pdev) } aspeed_adc_compensation(indio_dev); - /* Start all channels in normal mode. */ - adc_engine_control_reg_val = - readl(data->base + ASPEED_REG_ENGINE_CONTROL); - adc_engine_control_reg_val |= ASPEED_ADC_CTRL_CHANNEL; + adc_engine_control_reg_val = readl(data->base + ASPEED_REG_ENGINE_CONTROL); + /* + * Enable channels for normal operation. For battery sensing capable + * controllers, the battery channel is handled separately and is not + * included in the normal channel enable mask. + */ + adc_engine_control_reg_val |= + aspeed_adc_enable_channels(aspeed_adc_get_active_channels(data)); + writel(adc_engine_control_reg_val, data->base + ASPEED_REG_ENGINE_CONTROL); --- base-commit: 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f change-id: 20260313-adc-479b0ab09bae Best regards, -- Billy Tsai