From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2DB211093179 for ; Fri, 20 Mar 2026 05:47:05 +0000 (UTC) Received: from boromir.ozlabs.org (localhost [127.0.0.1]) by lists.ozlabs.org (Postfix) with ESMTP id 4fcWm810mHz2yZ6; Fri, 20 Mar 2026 16:47:04 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; arc=none smtp.remote-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=lists.ozlabs.org; s=201707; t=1773985624; cv=none; b=BBSqJUTaVKEgApFpAV6IZy3PerBfQ5j2BvqLIe3jqsJ+EchwP/ZyQfd8sg5E8Wuh2sCQu0Ja6NEaKJCOMyfb5gRY3sW3N8KHl2IHSEGe8tyDl218s7rHHPByv5DR4w799PXg/b3mOmx0BJ/FgF1OIrjCZmQqYgcpNSd7Rncxrb9mUkhtQemw9vb0sCir/yx/Mj9JKaxL49H9aCXoqC7C1ecOdhg+BYfDCajZ8w69wCpJetydpA2z2fYoOoiVWhL6PZPtZRT+zpH+Up6jBsc9F2Ad1x4qHU3HnZqtgz/fUAj7A9LT6Xlvfq/54F3OxrgtnrE7meb+LjEzYuQOWdQn3Q== ARC-Message-Signature: i=1; a=rsa-sha256; d=lists.ozlabs.org; s=201707; t=1773985624; c=relaxed/relaxed; bh=/77siN4XvlP7psojX88EZkW/Muy1TQhKbaSr1khUiHU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=PhZcl0pEQB1STAlTa6jZtHMwrX6gw/8vC7jsc7zQDlJSn6AIW29XuWirj+ZI5VhTgSOB9dSGI8Zae/qj2E/5TsPI6G21qwzxu/OPRfmGD0l6LaPbZBH6ZbzOCX8hYmNQhtGzSTE64zXArEpWV0qY4kBzbrogA4XC0Fxv9Tj1V4WN0zLn+ZCQgN8momCvaRJ50NgXqRiGDsgQP8eTxWR4UDRso3mDtWDFWSJEltgcmHY9qqUFa21ygyd/iJb+zAvnJ1+v/GTDAVNOHeN4kYeKVot8xbdLVY8PPv2te8cgh2wsJThCJzqdG8WeRq1MpKgzc4eBfSPC+4eD9mzIOSKoJA== ARC-Authentication-Results: i=1; lists.ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass (client-ip=211.20.114.72; helo=twmbx01.aspeed.com; envelope-from=billy_tsai@aspeedtech.com; receiver=lists.ozlabs.org) smtp.mailfrom=aspeedtech.com Authentication-Results: lists.ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=aspeedtech.com (client-ip=211.20.114.72; helo=twmbx01.aspeed.com; envelope-from=billy_tsai@aspeedtech.com; receiver=lists.ozlabs.org) Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4fcWm72V7Hz2yWK for ; Fri, 20 Mar 2026 16:47:03 +1100 (AEDT) Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 20 Mar 2026 13:46:40 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Fri, 20 Mar 2026 13:46:40 +0800 From: Billy Tsai Date: Fri, 20 Mar 2026 13:46:38 +0800 Subject: [PATCH v3 4/4] iio: adc: aspeed: Reserve battery sensing channel for on-demand use X-Mailing-List: linux-aspeed@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20260320-adc-v3-4-bc0eac04ef7c@aspeedtech.com> References: <20260320-adc-v3-0-bc0eac04ef7c@aspeedtech.com> In-Reply-To: <20260320-adc-v3-0-bc0eac04ef7c@aspeedtech.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , "Andy Shevchenko" , Joel Stanley , Andrew Jeffery CC: , , , , , Billy Tsai X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773985600; l=3092; i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id; bh=/PC/NyBFthLGN9cW7uymrG04TM1B2jgffJp1BtJPzvk=; b=RB0NDy13+uaIk/DhgVlJNMyfDOujB1yWJsODg/DzzJixBX0EPQO4bj3PrRMZ6FyO9JwEA9sjk oZj077hCYySDDdpXtifv5kTKDBB2UvkJ3EWbmhtBLqw2kADoQ7YRzNB X-Developer-Key: i=billy_tsai@aspeedtech.com; a=ed25519; pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ= For controllers with battery sensing capability (AST2600/AST2700), the last channel uses a different circuit design optimized for battery voltage measurement. This channel should not be enabled by default along with other channels to avoid potential interference and power efficiency issues. This ensures optimal power efficiency for normal ADC operations while maintaining full functionality when battery sensing is needed. Signed-off-by: Billy Tsai --- drivers/iio/adc/aspeed_adc.c | 34 +++++++++++++++++++++++++++++----- 1 file changed, 29 insertions(+), 5 deletions(-) diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c index a1a6296d3003..b3dee172adbf 100644 --- a/drivers/iio/adc/aspeed_adc.c +++ b/drivers/iio/adc/aspeed_adc.c @@ -138,6 +138,13 @@ static inline u32 aspeed_adc_channels_mask(unsigned int num_channels) static inline unsigned int aspeed_adc_get_active_channels(const struct aspeed_adc_data *data) { + /* + * For controllers with battery sensing capability, the last channel + * is reserved for battery sensing and should not be included in + * normal channel operations. + */ + if (data->model_data->bat_sense_sup) + return data->model_data->num_channels - 1; return data->model_data->num_channels; } @@ -305,9 +312,26 @@ static int aspeed_adc_read_raw(struct iio_dev *indio_dev, switch (mask) { case IIO_CHAN_INFO_RAW: + adc_engine_control_reg_val = readl(data->base + ASPEED_REG_ENGINE_CONTROL); + /* + * For battery sensing capable controllers, we need to enable + * the specific channel before reading. This is required because + * the battery channel may not be enabled by default. + */ + if (data->model_data->bat_sense_sup && + chan->channel == ASPEED_ADC_BATTERY_CHANNEL) { + u32 ctrl_reg = adc_engine_control_reg_val & ~ASPEED_ADC_CTRL_CHANNEL; + + ctrl_reg |= ASPEED_ADC_CTRL_CHANNEL_ENABLE(chan->channel); + writel(ctrl_reg, data->base + ASPEED_REG_ENGINE_CONTROL); + /* + * After enable a new channel need to wait some time for ADC stable + * Experiment result is 1ms. + */ + fsleep(1000); + } + if (data->battery_sensing && chan->channel == ASPEED_ADC_BATTERY_CHANNEL) { - adc_engine_control_reg_val = - readl(data->base + ASPEED_REG_ENGINE_CONTROL); writel(adc_engine_control_reg_val | FIELD_PREP(ASPEED_ADC_CH7_MODE, ASPEED_ADC_CH7_BAT) | @@ -321,11 +345,11 @@ static int aspeed_adc_read_raw(struct iio_dev *indio_dev, *val = readw(data->base + chan->address); *val = (*val * data->battery_mode_gain.mult) / data->battery_mode_gain.div; - /* Restore control register value */ - writel(adc_engine_control_reg_val, - data->base + ASPEED_REG_ENGINE_CONTROL); } else *val = readw(data->base + chan->address); + /* Restore control register value */ + writel(adc_engine_control_reg_val, + data->base + ASPEED_REG_ENGINE_CONTROL); return IIO_VAL_INT; case IIO_CHAN_INFO_OFFSET: -- 2.34.1