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Wed, 8 Apr 2026 13:31:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775655076; bh=sqUO8WthhJzcAvxM38OAUGehd9oMK+15WBmzaWNn1p0=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=rtN7MGYBrPtoBdayEGA8Bnd5JDJvLqhc+pJsd5pw0aUN5CcVQ2NLuFngCfmnH5qv0 iefrYkl1O+7pu18psbX3QN8D4M0iDwlJ3909aUSS3aPVNKUtF8YAB06ZiNj+G57h7X EUDkawGKS+itWyQRGJCn2GDmU1bBZhnRusnH+GDjHj0JvVBlCS7LJMSfU+zpH2Vsc+ nZlsRiPeyTA9ygmbXB5NjRNzIRCxFmhRDmrZd6yAzzu87c5hIJ5tF2SooEn+uLHLD3 tfvz6+2KrpaupePD8ZBHGDPh7tHbtppsgqO6U7k05O8cKHBGKlZdzds0DfddJ35sX0 1M1uXixj4VREA== Date: Wed, 8 Apr 2026 08:31:14 -0500 From: Rob Herring To: Billy Tsai Cc: Krzysztof Kozlowski , Lee Jones , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Linus Walleij , Bartosz Golaszewski , Ryan Chen , Andrew Jeffery , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-aspeed@lists.ozlabs.org" , "linux-kernel@vger.kernel.org" , "openbmc@lists.ozlabs.org" , "linux-gpio@vger.kernel.org" , "linux-clk@vger.kernel.org" Subject: Re: [PATCH v5 2/3] dt-bindings: mfd: aspeed,ast2x00-scu: Describe AST2700 SCU0 Message-ID: <20260408133114.GA1938858-robh@kernel.org> References: <20260331-upstream_pinctrl-v5-0-8994f59ff367@aspeedtech.com> <20260331-upstream_pinctrl-v5-2-8994f59ff367@aspeedtech.com> <20260401-adept-zebra-of-bloom-5bb68b@quoll> X-Mailing-List: linux-aspeed@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Thu, Apr 02, 2026 at 06:14:06AM +0000, Billy Tsai wrote: > > > AST2700 consists of two interconnected SoC instances, each with its own > > > System Control Unit (SCU). The SCU0 provides pin control, interrupt > > > controllers, clocks, resets, and address-space mappings for the > > > Secondary and Tertiary Service Processors (SSP and TSP). > > > > > > Describe the SSP/TSP address mappings using the standard > > > memory-region and memory-region-names properties. > > > > > > Disallow legacy child nodes that are not present on AST2700, including > > > p2a-control and smp-memram. The latter is unnecessary as software can > > > access the scratch registers via the SCU syscon. > > > > > > Also allow the AST2700 SoC0 pin controller to be described as a child > > > node of the SCU0, and add an example illustrating the SCU0 layout, > > > including reserved-memory, interrupt controllers, and pinctrl. > > > > > > Signed-off-by: Billy Tsai > > > --- > > > .../bindings/mfd/aspeed,ast2x00-scu.yaml | 117 +++++++++++++++++++++ > > > 1 file changed, 117 insertions(+) > > > > > > diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml > > > index a87f31fce019..86d51389689c 100644 > > > --- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml > > > +++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml > > > @@ -46,6 +46,9 @@ properties: > > > '#reset-cells': > > > const: 1 > > > > > > + memory-region: true > > > + memory-region-names: true > > > Missing constraints. From where did you take such syntax (so I can fix > > it)? > > The intention was to constrain these properties conditionally for > AST2700 SCU0 as done further down in the patch. > > I can update the binding so that memory-region and memory-region-names > have baseline constraints (e.g. minItems and maxItems), and then refine them in the > conditional branches for AST2700SCU0, AST2700SCU1 and others > > memory-region: > minItems: 2 > maxItems: 3 > memory-region-names: > minItems: 2 > maxItems: 3 As of this patch, you don't need that. You can just define the regions and names at the top-level. And the conditional schema only needs to disallow them for the appropriate case. Rob