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Tue, 21 Apr 2026 18:39:58 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id BFA0EC2BCB0; Tue, 21 Apr 2026 18:39:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776796798; bh=50mQHD7FkIRq1YWjICck6T5+Oufmi7QsAhgPHeR0pvM=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=XVpdSQ+RtzY6DXBIz5P+utA5Jm+7IvW1PJQT0HkIe/aJYAxaBs6mx5s7PC1H/eCxB ikORpKU+Q5q4nBMfp1sFBgudE5UUmEDscUk7yz0HcDBbRxu/Ay1JridC4AKWyz16aC 44Qadg1bUgmus5YzYKdBb4gszgRrBK6hFXg/jwT2Kl51bCFQL44nfEVJ9d9VekL5ft f7LuIifWK+dT8Rsll3YKDiRc8V2+EYyLn6JcXJTXz9usahPwOjSo/h41ryystRCAx7 uVlNZUwaZvV7BLC01XAAJUXzXL7YDQXDDbTUGYw/7PlgI7H8acD+u8h8awdRl2xnRW 3rhxJIhuN8cEA== Date: Tue, 21 Apr 2026 13:39:55 -0500 From: Rob Herring To: Billy Tsai Cc: Lee Jones , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Linus Walleij , Bartosz Golaszewski , Ryan Chen , Andrew Jeffery , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org, linux-gpio@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH v7 2/3] dt-bindings: mfd: aspeed,ast2x00-scu: Describe AST2700 SCU0 Message-ID: <20260421183955.GA1448377-robh@kernel.org> References: <20260416-upstream_pinctrl-v7-0-d72762253163@aspeedtech.com> <20260416-upstream_pinctrl-v7-2-d72762253163@aspeedtech.com> X-Mailing-List: linux-aspeed@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260416-upstream_pinctrl-v7-2-d72762253163@aspeedtech.com> On Thu, Apr 16, 2026 at 03:29:44PM +0800, Billy Tsai wrote: > AST2700 consists of two interconnected SoC instances, each with its own > System Control Unit (SCU). The SCU0 provides pin control, interrupt > controllers, clocks, resets, and address-space mappings for the > Secondary and Tertiary Service Processors (SSP and TSP). > > Describe the SSP/TSP address mappings using the standard > memory-region and memory-region-names properties. > > Disallow legacy child nodes that are not present on AST2700, including > p2a-control and smp-memram. The latter is unnecessary as software can > access the scratch registers via the SCU syscon. > > Also allow the AST2700 SoC0 pin controller to be described as a child > node of the SCU0, and add an example illustrating the SCU0 layout, > including reserved-memory, interrupt controllers, and pinctrl. > > Signed-off-by: Billy Tsai > --- > .../bindings/mfd/aspeed,ast2x00-scu.yaml | 113 +++++++++++++++++++++ > 1 file changed, 113 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml > index a87f31fce019..215ff59b38ea 100644 > --- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml > +++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml > @@ -46,6 +46,17 @@ properties: > '#reset-cells': > const: 1 > > + memory-region: > + items: > + - description: Region mapped through the first SSP address window. > + - description: Region mapped through the second SSP address window. > + - description: Region mapped through the TSP address window. blank line > + memory-region-names: > + items: > + - const: ssp-0 > + - const: ssp-1 > + - const: tsp > + > patternProperties: > '^p2a-control@[0-9a-f]+$': > description: > > @@ -87,6 +98,7 @@ patternProperties: > - aspeed,ast2400-pinctrl > - aspeed,ast2500-pinctrl > - aspeed,ast2600-pinctrl > + - aspeed,ast2700-soc0-pinctrl > > required: > - compatible > @@ -156,6 +168,30 @@ required: > - '#clock-cells' > - '#reset-cells' > > +allOf: > + - if: > + properties: > + compatible: > + contains: > + anyOf: > + - const: aspeed,ast2700-scu0 > + - const: aspeed,ast2700-scu1 More simply expressed as: contains: enum: - aspeed,ast2700-scu0 - aspeed,ast2700-scu1 > + then: > + patternProperties: > + '^p2a-control@[0-9a-f]+$': false > + '^smp-memram@[0-9a-f]+$': false