From: Andrew Lunn <andrew@lunn.ch>
To: 謝政吉 <kylehsieh1995@gmail.com>
Cc: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, Joel Stanley <joel@jms.id.au>,
Andrew Jeffery <andrew@codeconstruct.com.au>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] ARM: dts: aspeed: ventura2: Add Meta ventura2 BMC
Date: Tue, 23 Dec 2025 10:13:38 +0100 [thread overview]
Message-ID: <35f3eba9-5ec4-4cba-8a64-fb521dc65b79@lunn.ch> (raw)
In-Reply-To: <CAF7HswN_jEXOU_9K4LpLnbhvd+RD0qqELAHxMBbp=hGtMjS4kQ@mail.gmail.com>
On Tue, Dec 23, 2025 at 09:49:02AM +0800, 謝政吉 wrote:
> On Mon, Dec 22, 2025 at 5:30 PM Andrew Lunn <andrew@lunn.ch> wrote:
> >
> > > +&mdio0 {
> > > + status = "okay";
> > > +};
> > > +
> > > +&mac2 {
> > > + status = "okay";
> > > + phy-mode = "rmii";
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_rmii3_default>;
> > > + fixed-link {
> > > + speed = <100>;
> > > + full-duplex;
> > > + };
> > > +};
> >
> > That is an odd combination. You enable the MDIO bus, but don't have
> > any PHYs on it, no phandles pointing to it. And you have this
> > fixed-link. It makes me think you have an Ethernet switch on the bus,
> > and this connects to it?
> Thanks for the clarification.
> Yes, there is an Ethernet switch in the design.
> The MAC is connected to the switch via RMII using a fixed-link
> configuration.
What make/model of switch is it? Is it unmanaged, or does it use SPI
or I2C for management?
Andrew
next prev parent reply other threads:[~2025-12-23 9:14 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-22 7:45 [PATCH 0/2] Add Meta(Facebook) ventura2 BMC(AST2600) Kyle Hsieh
2025-12-22 7:45 ` [PATCH 1/2] dt-bindings: arm: aspeed: add Meta ventura2 board Kyle Hsieh
2025-12-23 13:54 ` Krzysztof Kozlowski
2025-12-22 7:45 ` [PATCH 2/2] ARM: dts: aspeed: ventura2: Add Meta ventura2 BMC Kyle Hsieh
2025-12-22 9:30 ` Andrew Lunn
2025-12-23 1:49 ` 謝政吉
2025-12-23 9:13 ` Andrew Lunn [this message]
2025-12-23 9:26 ` Kyle Hsieh
2025-12-23 10:35 ` Andrew Lunn
2025-12-24 6:40 ` Kyle Hsieh
2025-12-24 9:20 ` Andrew Lunn
2025-12-30 1:02 ` Kyle Hsieh
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