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Thu, 12 Jun 2025 10:18:06 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5B242C4CEED; Thu, 12 Jun 2025 10:17:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749723485; bh=haHjCLuyFcjjryC0APdEnmv4gb5nv2DCaiXwfEunHJM=; h=Date:Subject:To:References:From:In-Reply-To:From; b=dQYFqmGYD9dnEMLAaX7tWl8uJkb68MH4h4zEji8ux2NVi9l54qh4m/jwWVlvrh42N Z0hrv/Pjkmc462Dn8jaSdyvjs0ya6fhOO2DIgU7kc15G7zvA5lNzEwP9tdnlKhDEx7 gy8fnMRvJOnWAHqgvOe6/9tImJ/TrlyT9Jw8Gsesp3YRyic7RCyqfFys4N5WxHtZdE E/QwbElGUCd9Z3ff4kvXszezEmgX2tn52SPjBhHiPRq7sCEbsn/xEjTWFvpFli4K3j hAuTNHUltzD9fd8DM5VAhmx9UJSs88tSp0nyKCB40cpP+Jy/1DzXFm5RvNFezFingB XmOTOgl8MHq9A== Message-ID: <485749d4-b3c4-4965-9714-ad534d37e8c9@kernel.org> Date: Thu, 12 Jun 2025 12:17:57 +0200 X-Mailing-List: linux-aspeed@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device tree To: Ryan Chen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Catalin Marinas , Will Deacon , Arnd Bergmann , Bjorn Andersson , Geert Uytterhoeven , Nishanth Menon , nfraprado@collabora.com, Taniya Das , Lad Prabhakar , Kuninori Morimoto , Eric Biggers , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, soc@lists.linux.dev, Mo Elbadry , Rom Lemarchand , William Kennington , Yuxiao Zhang , wthai@nvidia.com, leohu@nvidia.com, dkodihalli@nvidia.com, spuranik@nvidia.com References: <20250612100933.3007673-1-ryan_chen@aspeedtech.com> <20250612100933.3007673-4-ryan_chen@aspeedtech.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 12/06/2025 12:09, Ryan Chen wrote: > This add the initial device tree support for the ASPEED AST2700 SoC. > > - Add top-level compatible string "aspeed,ast2700" and set up > address-cells/size-cells for 64-bit address space. > - Describe a quad-core ARM Cortex-A35 CPU cluster with L2 cache, > including cache properties and PSCI enable-method. > - Add PMU and ARMv8 timer nodes with correct PPI interrupt wiring. > - Model the dual-SoC architecture with two simple-bus nodes: > soc0 (@0x10000000) and soc1 (@0x14000000). > - Add syscon nodes for both SoCs (syscon0, syscon1) with clock/reset > cell definitions and address mapping. > - Add GICv3 interrupt controller node under soc0, with full register > mapping and interrupt properties. > - Hierarchical interrupt controller structure: > - intc0 under soc0, with child intc0_11 node. > - intc1 under soc1, with child intc1_0~intc1_5 nodes. > - Add serial4 node under soc0, others serial node under soc1. > > Signed-off-by: Ryan Chen > --- > arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi | 380 ++++++++++++++++++++++ > 1 file changed, 380 insertions(+) > create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi > > diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi > new file mode 100644 > index 000000000000..d197187bcf9f > --- /dev/null > +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi > @@ -0,0 +1,380 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later > +#include > +#include > +#include > + > +/ { > + #address-cells = <2>; > + #size-cells = <1>; > + interrupt-parent = <&gic>; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a35"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + i-cache-size = <0x8000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + next-level-cache = <&l2>; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a35"; > + enable-method = "psci"; > + reg = <0x0 0x1>; > + i-cache-size = <0x8000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + next-level-cache = <&l2>; > + }; > + > + cpu2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a35"; > + enable-method = "psci"; > + reg = <0x0 0x2>; > + i-cache-size = <0x8000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + next-level-cache = <&l2>; > + }; > + > + cpu3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a35"; > + enable-method = "psci"; > + reg = <0x0 0x3>; > + i-cache-size = <0x8000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + next-level-cache = <&l2>; > + }; > + > + l2: l2-cache0 { > + compatible = "cache"; > + cache-level = <2>; > + cache-unified; > + cache-size = <0x80000>; > + cache-line-size = <64>; > + cache-sets = <1024>; > + }; > + }; > + > + arm-pmu { > + compatible = "arm,cortex-a35-pmu"; > + interrupts = ; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = , > + , > + , > + ; > + arm,cpu-registers-not-fw-configured; > + always-on; > + }; > + > + soc0: soc@10000000 { > + compatible = "simple-bus"; > + reg = <0x0 0x10000000 0x10000000>; > + #address-cells = <2>; > + #size-cells = <1>; > + ranges; > + > + syscon0: syscon@12c02000 { > + compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd"; > + reg = <0x0 0x12c02000 0x1000>; > + ranges = <0x0 0x0 0 0x12c02000 0x1000>; > + #address-cells = <2>; > + #size-cells = <1>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > + gic: interrupt-controller@12200000 { > + compatible = "arm,gic-v3"; > + reg = <0 0x12200000 0x10000>, /* GICD */ > + <0 0x12280000 0x80000>, /* GICR */ > + <0 0x40440000 0x1000>; /* GICC */ > + #interrupt-cells = <3>; > + interrupt-controller; > + interrupts = ; > + interrupt-parent = <&gic>; > + }; > + > + serial4: serial@12c1a000 { > + compatible = "ns16550a"; > + reg = <0x0 0x12c1a000 0x1000>; > + clocks = <&syscon0 SCU0_CLK_GATE_UART4CLK>; > + interrupts = ; > + reg-shift = <2>; > + status = "disabled"; > + }; > + }; > + > + soc1: soc@14000000 { > + compatible = "simple-bus"; > + reg = <0x0 0x14000000 0x10000000>; > + #address-cells = <2>; > + #size-cells = <1>; > + ranges; > + > + syscon1: syscon@14c02000 { > + compatible = "aspeed,ast2700-scu1", "syscon", "simple-mfd"; > + reg = <0x0 0x14c02000 0x1000>; > + ranges = <0x0 0x0 0x0 0x14c02000 0x1000>; > + #address-cells = <2>; > + #size-cells = <1>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > + serial12: serial@14c33b00 { > + compatible = "ns16550a"; > + reg = <0x0 0x14c33b00 0x100>; > + clocks = <&syscon1 SCU1_CLK_GATE_UART12CLK>; > + interrupts-extended = > + <&intc1_4 18 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > + reg-shift = <2>; > + status = "disabled"; > + }; > + }; > +}; > + > +&soc0 { This is the base DTSI, there is no existing node to override. Just define complete SoC node in one place like every other vendor. > + intc0: interrupt-controller@12100000 { > + compatible = "simple-mfd"; NAK, never tested. Not allowed, see bindings. And test it next time. Best regards, Krzysztof